Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
Planar Fully-Depleted (FD) Silicon On Insulator (SOI) MOSFET technology has already demonstrated large performance boost vs bulk at 28nm node (>30%) and is very competitive for incoming mobile & multimedia products thanks to design porting from bulk. Indeed, FDSOI is very attractive for low power applications due to its low sub threshold slope (~60mV/dec), better short channel effect (SCE) control and reduced junction capacitance. 28nm FDSOI devices highly depend on gate CD morphology because electrical effective gate length is driven by metal gate CD. High-k metal gate etching is therefore a key point to achieve these requirements. Gate profiles and metal gate CD control are mandatory and variability has to be minimized across the wafer (WiW), wafer to wafer and lot to lot. In this paper, we will focus on metal gate CD variability investigation. Once polysilicon gate profiles are frozen, metal gate profiles adjustment is achieved, based on scatterometry metal gate profiles measurements, TEM analysis and electrical results. Thanks to this methodology, a metal gate etching process has been tuned on 300mm industrial platform etcher. This work was performed at ST Crolles 300 facility in collaboration between STMicroelectronics & CEA/LETI.
For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-LETI. We have demonstrated the integration of these alternative techniques in front end of line and back end of line levels. Common challenges such as minimum achievable CD, CD control through the integration steps, mask budget and LWR were compared for these techniques.
Gate patterning control for 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology faces several challenges. For lithography and etch , usage of DoseMapper requires extensive and accurate metrology to compute adequate dose recipes. From etch side we will have to control both polysilicon and metal gate CD’s. For device integration it will be extremely important to monitor N and PMOS devices and get appropriate gate profiles since transistor morphology is a key contributor to device performances. In parallel of CD control, thin silicon film on top of buried oxide layer will also require a strict control of its thickness. Scatterometry is the only way to get all these informations from a patterned environment . We will show in this paper how scatterometry has been proven to be accurate enough to support the realization of DOE’s for metal gate profile optimisation at gate patterning without doing hundred’s of TEM. Scatterometry results are correlated to parametric tests and TEM for ultimate validation.