Mask data which can not be properly resolved by the mask writing tools, such as sub(resolution (reticle-scale) features or
singularities can interfere with design intent or manufacturing capabilities in the absence of design guidelines or formal
verification procedures. As a consequence, mask writing tools may introduce defects to device or metrology structures
by snapping geometries to grid or misrepresenting process based sizing. To reduce the visibility of these defects by
detuning inspection tools to release the mask with non-resolvable data in the production cycle or by waiving minimum
CD rules compromises high fidelity of die pattern transfer to wafer. Driven by poor data quality, mask tool would
provide degraded resolution without contextual analysis, such as correlations to the overlying and underlying mask
layers and without regard to device models. The key reasons for this situation are arbitrary layout of technology
structures and design layout-to-mask post-processing for OPC and fill pattern for which design has no intention or
knowledge to intervene. The post-processing of mask data to eliminate errors effectively detaches design responsibility
from the mask shop actions and may have other detrimental effects on the production cycle such as iterative defect
analysis and long write times due to the large polygon count. In this work we propose mask rule check based on the
principles to which the masks are being written and inspected. Running this mandatory rule set should reduce the
product cycletime, benefit the cost and improve mask quality and reproduction of design intent. It feeds the prospective
mask information back to the layout time making it possible to make design adjustments in the interest of pattern fidelity
and device parameters.
One of Cypress’ primary goals for 90-nm generation mask strategy is to control mask costs while not compromising on performance. One key objective is to replace the use of 50-ke V electron beam pattern generation with DUV laser mask lithography where possible. The higher productivity of the DUV laser systems compared to the 50Ke V e-beam platforms offers a unique opportunity for mask cost reduction. Compared to previous i-line generations of laser lithography systems, the DUV laser systems provide significantly improved resolution and pattern fidelity that more closely approaches that of ebeam lithography. We have previously published experimental results demonstrating that the difference in fidelity on the mask between the laser and EB platforms does not always translate to a measurable difference in wafer litho performance or even more importantly to a measurable difference in electrical performance. Through this work, Cypress was able to eliminate the use of 50Ke V ebeam writers for all of their 130nm technology node layers. In some cases the improved performance of the DUV tools was sufficient to replace i-line produced masks where wafer performance was marginal without having to resort to EB lithography. This study addresses the conversion of 50Ke V ebeam layers to DUV laser platform specifically for the critical layers of the Cypress’ 90nm Technology node. EB lithography was originally specified for these layers as a conservative approach in part due to the timing of 90-nm technology development relative to the maturation of the DUV laser mask lithography process. In this study, the electrical performance and wafer yield are evaluated for equivalency in order to take advantage of the lower cost and faster cycletime that use of a ALTA DUV system provides over the 50Ke V VSB systems. In addition, the wafer OPC is not changed between the two mask writing systems in order to allow interchangeable use of the two writing systems if the experimental results indicated no difference in wafer performance.
Mask CD resolution and uniformity requirements for back end of line (BEOL) layers for the 90nm Technology Node push the capability of I-line mask writers; yet, do not require the capability offered by more expensive 50KeV ebeam mask writers. This suite of mask layers seems to be a perfect match for the capabilities of the DUV mask writing tools, which offer a lower cost option to the 50KeV platforms.
This paper will evaluate both the mask and wafer results from all three platforms of mask writers (50KeV VSB,ETEC Alta 4300TM DUV laser and ETEC Alta 3500TM I-line laser) for a Cypress 90nm node Metal 1 layer, and demonstrate the benefits of the DUV platform with no change to OPC for this layer.
The integration of 193nm Lithography is close to full production for the 90nm node technology. With the potential of emerging 193nm lithographic resolution down to 65nm, the quality of 193nm reticles including binary, EAPSM and AAPSM must be outstanding so that low K1 factor reticles may be used in production. One area of concern in the IC industry is haze contamination on the mask once the reticle has been exposed to ArF radiation. In this study, haze was found outside of the pellicle and on the quartz side of the mask. Standard through-pell inspections will typically miss the contamination, yet its severity can ultimately affect mask transmission. For this reason, DuPont Photomasks and Cypress joined forces to quickly decipher how it develops. In this investigation, tests were devised which altered conditions such as mask environment, exposure, traditional and advanced cleaning chemistry. This paper describes the relationship between surface and environmental photochemical reactions, the resultant growth, analysis, and how it is controlled.
It has long been understood that there is an image fidelity difference between the integrated circuit design pattern and the photomask made from that pattern, largely due to the finite spot size of pattern generators. Furthermore, there are known differences in photomask image fidelity (rounding, jogs, etc.) between e-beam and laser pattern generators. Using a novel technique developed by DuPont Photomasks, Inc. (DPI), actual photomask fidelity has been simulated from design data to produce a more true-to-life representation of the mask. We have performed analytical simulations and printed-wafer measurements on Cypress 100-nm technology designs to determine the differences and effects on optical proximity correction (OPC) of two types of pattern generators: 50 keV e-beam and DUV laser. Both JEOL 9000MV-II+ and ETEC ALTA 4000 images were simulated and saved in GDSII format (“mask-GDSII”). These new mask images were processed through standard lithography simulation software to predict the effects each mask writer has on localized optical proximity effects. Simulations were compared to printed wafer results. A detailed comparison of the accuracy of the mask-GDSII and original design GDSII is performed. Furthermore, comparison of 50 keV e-beam and DUV laser image fidelity is completed, and recommendations are made on how to correct OPC models for each type of photomask generator. Lastly, conclusions are drawn about the use of DUV laser and 50 keV e-beam photomasks.
The semiconductor industry continues to aggressively shrink linewidths and manufacture more closely spaced patterns to improve power and speed performances, as well as increase die per wafer counts. Current development is near 100 nm and high volume manufacturing is commonly near 150 nm. These smaller linewidths and more dense patterns are hampered with new populations of defects that were previously unimportant second or third order effects. As a result, new defects of interest must specifically be investigated, detected, and prevented on the reticles that hold master images of what is being printed. This is often difficult because reticle manufacturing, reticle defect detection, and reticle end-usage (manufacturer) typically spans three corporations. If defects occur on wafers that were not detected with current reticle inspection capabilities, there must be correlation from the printed wafer back to the reticle to assist the reticle supplier in locating the defect and working towards eliminating the problem. In some cases, photo defects may not impact device functionality. As a result closed-loop analyses and actions, which determine whether an event actually causes yield loss, must be developed into the business practices of multiple companies. This paper reports on an inter-company process (ICP) involving Cypress Semiconductor Corporation, Dupont Photomask Incorporated, and KLA-Tencor. The ICP evaluates reticle defects on wafers, their impact on yield, and the transfer of the defect information back to the reticle vendor in an effort to improve overall reticle quality for a 150 nm and beyond semiconductor manufacturing fab.