While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system’s sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.
In 2009 a new European initiative on Double Patterning and Double Exposure lithography process development was
started in the framework of the ENIAC Joint Undertaking. The project, named LENS (Lithography Enhancement
Towards Nano Scale), involves twelve companies from five different European Countries (Italy, Netherlands, France,
Belgium Spain) and includes: IC makers (Numonyx and STMicroelectronics), a group of equipment and materials
companies (ASML, Lam Research srl, JSR, FEI), a mask maker (Dai Nippon Photomask Europe), an EDA company
(Mentor Graphics) and four research and development institutes (CEA-Leti, IMEC, Centro Nacional de
The LENS project aims to develop and integrate the overall infrastructure required to reach patterning resolutions
required by 32nm and 22nm technology nodes through the double patterning and pitch doubling technologies on existing
conventional immersion exposure tools, with the purpose to allow the timely development of 32nm and 22nm
technology nodes for memories and logic devices, providing a safe alternative to EUV, Higher Refraction Index Fluids
Immersion Lithography and maskless lithography, which appear to be still far from maturity.
The project will cover the whole lithography supply chain including design, masks, materials, exposure tools, process
integration, metrology and its final objective is the demonstration of 22nm node patterning on available 1.35 NA
immersion tools on high complexity mask set.
Full wafer dual beam FIB-SEM systems have received a lot of industrial interest in the last years and by now are operational in several 200mm and 300mm fabs. These tools offer a 3D-physical characterization capability of defects and device structures and as such allow for more rapid yield learning and increased process control. Moreover, if SEM resolution is insufficient to reveal defect origin or the necessary process details, it is now also possible to prepare TEM samples using a controlled, easy to learn in-situ process and to efficiently continue the characterization with a high resolution TEM inspection. Thanks to latest hardware developments and the high degree of automation of this TEM sample preparation process, wafers no longer need to be broken and remain essentially free from contamination. Hence, the TEM lamella process can be considered as non-destructive and wafers may continue the fabrication process flow.
In this paper we examine the SEM and TEM application capabilities offered by in-line dual beam systems. To qualify the wafer return strategy, the particle contamination generated by the system hardware as well as the process-induced contamination have been investigated. The particle levels measured are fully acceptable to adopt the wafer return strategy. Ga-contamination does exist but is sufficiently low and localized so that the wafer return strategy can be applied safely in the back-end of line process. Yield analysis has confirmed that there is no measurable impact on device yield. Although yet to be proven for the frond-end of line processes, the wafer return strategy has been demonstrated as a valuable one already in the backend of line processes. The as developed non-destructive 3-D SEM-TEM characterization capability does offer value added data that allow to determine the root cause of critical process defects in almost real-time and this for both standard (SEM) and more advanced (TEM) technologies.