For the next generation of HighThroughPut (HTP) Telecommunications Satellites, space end users’ needs will result in higher link speeds and an increase in the number of channels; up to 512 channels running at 10Gbits/s. By keeping electrical interconnections based on copper, the constraints in term of power dissipation, number of electrical wires and signal integrity will become too demanding. The replacement of the electrical links by optical links is the most adapted solution as it provides high speed links with low power consumption and no EMC/EMI.
But replacing all electrical links by optical links of an On Board Payload (OBP) is challenging. It is not simply a matter of replacing electrical components with optical but rather the whole concept and architecture have to be rethought to achieve a high reliability and high performance optical solution. In this context, this paper will present the concept of an Innovative OBP Optical Architecture.
The optical architecture was defined to meet the critical requirements of the application: signal speed, number of channels, space reliability, power dissipation, optical signals crossing and components availability. The resulting architecture is challenging and the need for new developments is highlighted. But this innovative optically interconnected architecture will substantially outperform standard electrical ones.
Thin-film computations are often a time-consuming task during optical design. An efficient way to accelerate these computations with the help of graphics processing units (GPUs) is described. It turned out that significant speed-ups can be achieved. We investigate the circumstances under which the best speed-up values can be expected. Therefore we compare different GPUs among themselves and with a modern CPU. Furthermore, the effect of thickness modulation on the speed-up and the runtime behavior depending on the input data is examined.
A parallel board-level interconnection design is presented consisting of 32 channels, each operating at 10 Gbps.
The hardware uses available optoelectronic components (VCSEL, TIA, pin-diodes) and a combination of planarintegrated
free-space optics, fiber-bundles and available MEMS-components, like the DMD™ from Texas Instruments.
As a specific feature, we present a new modular inter-board interconnect, realized by 3D fiber-matrix
connectors. The performance of the interconnect is evaluated with regard to optical properties and power consumption.
Finally, we discuss the application of the interconnect for strongly distributed system architectures,
as, for example, in high performance embedded computing systems and data centers.
Different mask models have been compared: rigorous electromagnetic field (EMF) modeling, rigorous EMF
modeling with decomposition techniques and the thin mask approach (Kirchhoff approach) to simulate optical
diffraction from different mask patterns in projection systems for lithography. In addition, each rigorous model
was tested for two different formulations for partially coherent imaging: The Hopkins assumption and rigorous
simulation of mask diffraction orders for multiple illumination angles. The aim of this work is to closely approximate
results of the rigorous EMF method by the thin mask model enhanced with pupil filtering techniques. The
validity of this approach for different feature sizes, shapes and illumination conditions is investigated.
We consider the implementation of a dynamic crossbar interconnect using planar-integrated free-space optics (PIFSO)
and a digital mirror-device™ (DMD). Because of the 3D nature of free-space optics, this approach is able to solve
geometrical problems with crossings of the signal paths that occur in waveguide optical and electrical interconnection,
especially for large number of connections. The DMD device allows one to route the signals dynamically. Due to the
large number of individual mirror elements in the DMD, different optical path configurations are possible, thus offering
the chance for optimizing the network configuration. The optimization is achieved by using an evolutionary algorithm
for finding best values for a skewless parallel interconnection. Here, we present results and experimental examples for
the use of the PIFSO/DMD-setup.
In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one
billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on
central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long
and too many global interconnects for the distribution of code or the access to common memory. On the other hand
nature developed self-organising and emergent principles to manage successfully complex structures based on lots of
interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm
based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present
different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a
0.18 &mgr;m CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100
MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow
the integration and processing of Mega pixels within the same time since our architecture is fully scalable.
We present a fine-grain parallel processor architecture which considers particularly the requirements defined by future 3-dimensional (3D) stacked optoelectronic devices. The architecture concept is well-suited for novel detector arrays which are exploited in data communication applications based on high-speed VCSEL photonic interconnects as well as for optical sensing applications in smart CMOS camera chips. We assume the presence of a two-dimensional optoelectronic interface mounted on top of the stacked device. Such a vertical communication scheme is perfect for the realization of very compact and fast working devices in embedded systems, e.g. in gripper arms of robots.
We present a chip, which is suited for applications in data-communication areas as well as in image-processing applications. Through the combination of parallel signal gathering and processing, we save components and we can increase the processing rate. We think thereby on problems like pre processing in camera systems also called "intelligent sensor". The chip has a structure as follows. Every processor element contains an optical detector, a trans-impedance amplifier and a comparator. A digital logic is directly connected to these components. This logic realizes the programmable processing of the signals. Each processor element is connected to its four direct orthogonal neighbours within the processor array. The digital parts consist of a special processor. It realises simple hard-wired image algorithms. As an example for cooperation of the analogue and digital part we have implemented some morphologic operations. Our receiver consists of a 8×8 photodiode array. A data rate of 625 Mbit/s for an average optical power in the range of 25 µW to 500 µW is possible for a bit-error-rate of 10-9 per channel. Signal processing limits the frequency to 200 MHz for a processor element according to simulations. Using an image with a size of 6×6 according to parallel data transfer a data throughput of 7.2 GHz results.
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8'8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 µm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.
We introduce an optoelectronic VLSI implementation of a parallel signal processor whose processing nodes receive their binary constant values by means of an optical interconnection network. The processing nodes are integrated in a fixed array raster. Each node requires its own optical inputs realized as smart-detector units. A smart-detector is a combination of an optical receiver device and a receiver circuit and transforms the optical information into electrical signals. We use integrated photo diodes as optical receivers. The photo diodes are optimized for fiber optical coupling and they can be integrated with standard mainstream CMOS/BiCMOS technology. The project is in progress and we present first results.
KEYWORDS: Digital signal processing, Clocks, Interfaces, Optoelectronics, Signal processing, Diodes, Very large scale integration, Optical interconnects, Computer architecture, Content addressable memory
Limited bandwidth because of too few and too slow external pins is one of the major problems in current VLSI systems. Increasing clock rates and the growing transistor density in future microprocessor will enlarge the imbalance between satisfying computing power and insufficient communication performance. Optoelectronic VLSI (OE-VLSI) circuits using highly dense 3D optical interconnections offer the potential to overcome these problems. To lead OE-VLSI processing to success it is necessary to point out a diversity of architectures that profit extremely from a 2D optical input/output interface. Such architectures have to be developed especially for an optoelectronic solution. We demonstrate this for various architectures like binary neural associative memories and fine-grain 3D processor cores for integer and digital signal processing. We specify the electronic circuits and the optical interconnection schemes. We found out that an optoelectronic approach for the associative memory offers two orders of magnitude more performance than all-electronic solutions. The stacked 3D integer processor offers a performance increase of about 10 to 50 over current RISC processors. For the realization of the OE-VLSI circuits we developed a CMOS-SEED chip and a smart detector test chip consisting of CMOS circuitry monolithically integrated with a silicon based array of photo diodes.
Hybrid SEED technology is used for the realization of a binary neuronal associative memory. The architecture profits from 200 parallel optical data channels available on top of the silicon. The project is in progress and we present first results.
The major problems in the current VLSI design are restrictions of both the number of available pins and the of-chip communication speed. The currently lasting process of increasing integration density of VLSI chips keeps these problems alive and still increases the difficulties respectively. Due to physical reasons the ability of a high speed off-chip communication in the same range of the on- chip communication is very difficult to achieve. Optoelectronic 3D circuits based on smart pixel technologies offer a principle solution for the problems mentioned above. We think for the success of optoelectronic computing it is very important to get flexible usable smart pixel circuits. Hence, we present an architecture design for programmable smart pixels. Our approach combines the functional flexibility of FPGAs with the advantages of optoelectronics providing fast and high dense optical interconnections. Moreover, this combination allows the design of various 3D processor element architectures by changing logical behavior and topology to get routing more simple and offering higher data throughput. After an overview of existing solutions we demonstrate a hardware approach of an ALU, based on a 3D free programmable SPPE array for the fast calculation of standard functions, e.g. exp, sin, cos,...furthermore we specify hardware relevant parameters.
The high data transfer requirements in digital computing demand the use of optics. The next step is to perform data
processing by optical or opto-clectronic devices. As with electronic computing this computer architecture needs computer
skied support. We present a software system which allows interactive design, simulation and evaluation of such computer
architectures. With this system, we have developed arithmetic units based on systolic arrays.