The aggressive device scaling imposed by the International Technology Roadmap for Semiconductors (ITRS) is
introducing additional and more demanding challenges to current in-line monitoring tools. In this paper we present a
new probe microscopy based technology, the Rapid Probe Microscope (RPM), which produces nano-scale images using
a height contrast mechanism in a non-vacuum environment. The system offers the possibility to address metrology
challenges in alternative ways to existing review and inspection tools. This paper presents applications of the RPM
process which cater to the requirements of the semiconductor industry. Results on several standard semiconductor wafer
layers have been used to demonstrate the capabilities of the RPM process, including nano-scale surface imaging at high
image capture rates.
New techniques recently developed at the National Institute of Standards and Technology using bright-field optical tools
are applied to signal-based defect analysis of features with dimensions well below the measurement wavelength. A key
to this approach is engineering the illumination as a function of angle and analysis of the entire scattered field. In this
paper we demonstrate advantages using this approach for die-to-die defect detection metrology. This methodology,
scatterfield optical microscopy (SOM), is evaluated for defect inspection of several defect types defined by Sematech on
the Defect Metrology Advisory Group (DMAG) intentional defect array (IDA) wafers. We also report the systematic
evaluation of defect sensitivity as a function of illumination wavelength.
Theoretical simulations are reported that were carried out using a fully three-dimensional finite difference time domain
(FDTD) electromagnetic simulation package. Comprehensive modeling was completed investigating angle-resolved
illumination to enhance the detection of several defect types from the IDA wafer designs. The defect types covered a
variety of defects from the IDA designs. The simulations evaluate the SOM technique on defect sizes ranging from
those currently measurable to those the industry considers difficult to measure. The simulations evaluated both the 65
nm IDA metal-1 M1 trench and the polysilicon stack and more recent 13 nm linewidth logic cells.
As Moore's Law indicates, pattern feature sizes have become smaller and smaller, increasing the need for more critical
metrology and inspection methodologies in integrated circuit fabrication. Critical methodologies are especially required
in the inspection area where more critical defect definition methods are needed for the accurate evaluation of inspection
In traditional defect definition, we have to use only normal CD measurement results with manual measurement methods.
This one dimensional definition method gives only defect size information which is not enough information to do
accurate evaluation. In addition, there is a lot of measurement uncertainty such as human errors, measurement errors,
and systematic errors which are included in the data of manual measurement methods. Because of these mentioned
issues, evaluation results will differ from person to person and other environmental influences.
In this paper, the defects will be defined not only with one dimensional measurement but also with two dimensional
measurements using such functions as Gap measurement and EPE (Edge Placement Error) measurement in
<b>DesignGauge</b> using <b>Design Data</b>. For example, misplacement defects in which a pattern is shifted on the wafer as
shown in figure 1 below; traditional one dimension measurement methods can not detect this type of defect. However,
with <b>DesignGauge</b>, misplacement defects can easily be detected if the <b>Design Data</b> is used as shown in figure 2. EPE
measurement method, which is one of the advanced features of <b>DesignGauge</b>, will accurately define misplacement
As the trends of smaller feature sizes in integrated circuit fabrication continues, various defects should be controlled and
measured with advanced defect definition methods using <b>Design Data</b>.
The conventional premise that metrology is a "non-value-added necessary evil" is a misleading and dangerous assertion,
which must be viewed as obsolete thinking. Many metrology applications are key enablers to traditionally labeled
"value-added" processing steps in lithography and etch, such that they can be considered integral parts of the processes.
Various key trends in modern, state-of-the-art processing such as optical proximity correction (OPC), design for
manufacturability (DFM), and advanced process control (APC) are based, at their hearts, on the assumption of fine-tuned
metrology, in terms of uncertainty and accuracy. These trends are vehicles where metrology thus has large opportunities
to create value through the engineering of tight and targetable process distributions. Such distributions make possible
predictability in speed-sorts and in other parameters, which results in high-end product. Additionally, significant reliance
has also been placed on defect metrology to predict, improve, and reduce yield variability. The necessary quality
metrology is strongly influenced by not only the choice of equipment, but also the quality application of these tools in a
production environment. The ultimate value added by metrology is a result of quality tools run by a quality metrology
team using quality practices.
This paper will explore the relationships among present and future trends and challenges in metrology, including
equipment, key applications, and metrology deployment in the manufacturing flow. Of key importance are metrology
personnel, with their expertise, practices, and metrics in achieving and maintaining the required level of metrology
performance, including where precision, matching, and accuracy fit into these considerations. The value of metrology
will be demonstrated to have shifted to "key enabler of large revenues," debunking the out-of-date premise that
metrology is "non-value-added." Examples used will be from critical dimension (CD) metrology, overlay, films, and
Without the ability to detect potential yield-limiting defects in-line, the yield learning cycle is severely crippled, compromising the financial success of chip makers. As design rules shrink, device yield is seriously affected by smaller size particle and patterned defects that were not important in the past. These mechanisms are becoming more difficult to detect with current defect detection tools and techniques. The optical defect inspection tools that are currently available do not adequately detect defects, while scanning electron microscope (SEM) based inspection tools are too slow. With each successive technology node, optical inspection becomes less capable relative to the previous technology. As sensitivity is increased to detect smaller defects, the nuisance defect rate increases commensurately. Line-edge roughness (LER) and subtle process variations are making it more difficult to detect defects of interest (DOI). Smaller defects mean smaller samples available for energy dispersive x-ray analysis (EDX), necessitating an improved or new methodology for elemental analysis. This paper reviews these and some other challenges facing defect metrology at the 45nm technology node and beyond. The challenges in areas of patterned and unpatterned wafer inspection, defect review, and defect characterization are outlined along with proposed solutions. It also provides an overview of several ongoing projects conducted at International SEMATECH Manufacturing Initiative (ISMI) to address these challenges.