As the semiconductor industry scales down to 90nm and below, Model-Based OPC has become a standard practice to
compensate for optical proximity effects and process variations occurring when printing features below the exposure
wavelength. For parametric OPC models, it is assumed that the empirical data are accurate and the model parameter
space is sufficiently well sampled. In spite of advanced metrology tools, the measurement uncertainty for 1D small
critical dimensions and 2D patterns remains to be a challenge. Traditionally, the weight of SEM measurement points are
based on either statistical method such as standard deviations, or engineers' judgment, which is either time consuming or
individual-dependent. In this paper, the slope-integrated OPC model calibration methodology is proposed, which takes
into account the slope as a weighting indicator. The additional measurement objects per calibration structure are
economically feasible, as most metrology tool time is spent on addressing and auto-focusing. When we consider one
measurement point with both CD and slope measurements, the slightly increased time is tolerable for FAB, which
requires a short turn around time (TAT). By this approach, we can distinguish measurement points with low confidence
from those accurate ones. Furthermore, we check the fitting differences among equal-weighted data sheets, empiricalweighted
data sheets and slope-weighted data sheets, by using the same variable threshold model form. From the edge
placement error (EPE) of fitting results and the overlap between simulated contours and SEM images, it is found that the
proposed slope-integrated methodology results in a more accurate and stable model.
The effectacy of the OPC model depends greatly on test pattern data calibration that accurately captures mask and wafer
processing characteristics. The CD deviation caused by an off-center mask process can easily consume the majority of
the lithography process CD budget. Mask manufacturing variables such as write tools' resolution, etch process effects,
and pre-bias of the fractured data have great impacts on OPC model performance. As a result, wafer performance using
masks from different mask shops varies due to variations in the mask manufacturing process, even if the masks are
written with the same data set and use the same manufacturing specifications. A methodology for mask manufacturing
calibration is proposed in order to make an OPC model consistent between two mask manufacturing processes. The
methodology consists of two parts: mask manufacturing calibration and wafer-level OPC accuracy verification. The
mask manufacturing process and metrology are calibrated separately. The OPC model is built based on the database of
the first-party mask shop, and OPC verification is carried out by wafer data using the newly calibrated mask from the
second-party mask shop. By checking wafer performance of both OPC model matrix items and complicated 2D
structures, the conclusion can be drawn that different mask shops can share the same OPC model with rigorous mask
calibration. This methodology leads to lower engineering costs, shorter turn around time (TAT) and robust OPC
Model-based Optical Proximity Correction (MBOPC) is used to make systematic modifications to transfer a pattern's design intent from a drawn database to a wafer. This is accomplished by manipulating the shape of mask features to generate the desired pattern (design intent) on the wafer. MBOPC accomplishes this task by dividing drawn patterns into segments, then using a process model to manipulate these segments to achieve the design intent on the wafer. The generation of an accurate process model is very important to the MBOPC process because it contains the process information used to manipulate correction segments. When corrected data are written on a reticle, the faithful and well-controlled reproduction of the data on the mask is critical to realizing the desired lithographic performance. This paper will explore methodologies to improve model accuracy using mask fabrication data and process test patterns. Model accuracy improvement will be accomplished using intelligent sampling plans and representative mask structures. The sampling plan needs to identify critical device and process features. The test mask used to generate the process model needs to have test structures to gather process data. The test mask also must have test structures that can evaluate model quality by testing the extrapolation and interpolation of the model to data that was no used to generate the process model. These methodologies will be shown to improve final mask pattern quality.
As the patterns are getting smaller, the difficulty to control a margin-tight process expands exponentially. The use of the Automated Process Control (APC), therefore, becomes a widely employed mean in photolithography process to control overlay and CD variations. The accuracy of APC is dependent upon the amount of the previous process data. However, in a foundry with high-mix products it is typical that there are not enough historic data points for accurate calculation of process parameters for a low volume product. The consequence is the high rework rate of pilot runs and test runes due to poor process parameter prediction for overlay. Several studies of the method for predicting the overlay correction have been reported. The key to build a good prediction model is to break the overlay errors down to several parts. Some are equipment or technology related errors, which are shared by all products. Others are the characteristic for certain products, for instance, mask error or special alignment marks. In the production environment the former parts are updated in real time by data feedback from processing all kinds of products. The low volume products or pilot products can share the information. Thus we can achieve a more accurate control or prediction for a new product. In this paper we provide a new model for predicting the process parameter settings of overlay for a pilot run or a product not being run on a tool for a long period of time. This new model is a Simplified Cerebellar Manipulation Arithmetic Controller (SCMAC), which is one kind of Neural Network (NN) model. We assume each part of overlay errors is a cell in SCMAC and build the whole cell table by using this assumption. The final overlay correction value is the sum of a group of cells, which is activated by one lot information. We will also present the details of the building and training of this new SCMAC model. The prediction accuracy of SCMAC in overlay parameters is also evaluated. According to the results, SCMAC can split the overlay error to several factors successfully and also overcome the mismatch in the equipments and processes. We also compare the new SCMAC model with the general Exponential Weighted Moving Average (EWMA) model, which calculates the correction value based on the history data points, and in which the newer data points have more weight in the calculation. Based on the results, the SCMAC model is not good enough to substitute the EWMA model in controlling the overlay of a high volume product.
Lithography Rule Check (LRC) becomes a necessary procedure for post OPC in 0.15μm LV and below technology in order to guarantee mask layout correctness. LRC uses a process model to simulate the mask pattern and compare its performance to the desired layout. When the results are out of specified tolerances, LRC will generate error flags as weak points to trigger further checks. This paper introduces LRC to detect the weak points even in non-OPC employed circuit layout such as 0.18μm to 0.15μm process. LRC is more important for semiconductor foundry since there are diverse design layouts and shrinks in production. This diversity leads to the possibility of problematic structures reaching the reticle. In this work, LRC is added as a necessary step in tape-out procedure for the sub 0.18μm process nodes. LRC detected weak points such as low or excessive contrast sites, high MEEF areas and small process window features, then modified the layout according to check results. Our work showed some mask related potential problems can be avoided by LRC in even non model based OPC process and therefore guarantee improved product yield.
Model-based Optical Proximity correction has become an indispensable tool for achieving wafer pattern to design fidelity at current manufacturing process nodes. Most model-based OPC is performed considering the nominal process condition, with limited consideration of through process manufacturing robustness. This study examines the use of off-target process models - models that represent non-nominal process states such as would occur with a dose or focus variation - to understands and manipulate the final pattern correction to a more process robust configuration. The study will first examine and validate the process of generating an off-target model, then examine the quality of the off-target model. Once the off-target model is proven, it will be used to demonstrate methods of generating process robust corrections. The concepts are demonstrated using a 0.13 μm logic gate process. Preliminary indications show success in both off-target model production and process robust corrections. With these off-target models as tools, mask production cycle times can be reduced.