Proc. SPIE. 6152, Metrology, Inspection, and Process Control for Microlithography XX
KEYWORDS: Lithography, Electron beam lithography, Metrology, 3D acquisition, Silicon, Atomic force microscopy, Scanning electron microscopy, 3D metrology, Critical dimension metrology, Semiconducting wafers
CD measurement bias has long been reported as an inherent artifact of CD-SEM measurements. However, as feature dimensions decrease and line-to-space ratios increase, the magnitude of previously acceptable levels of measurement bias requires re-examination. Traditional attempts at correcting the bias has entailed slow, destructive or laborious techniques, such as comparisons of top-down CD-SEM measurements using standard algorithms with cross-section information, or correlating top-down data with complex tilted images.
In this paper we expand the application of Critical Shape Metrology - a physics-based metrology technique for 3-D profile acquisition based on CD-SEM, to minimizing CD bias in real-time for a variety of feature dimensions and profiles. Samples used for the experiments were fabricated through E-Beam lithography and 193 lithography with a wide variation of sidewall angles and CDs, so that the measurement bias could be assessed over a sufficiently large range of patterned shapes. Reference measurements were performed using a CD-AFM and FIB-SEM
Critical Shape Metrology (CSM), a Monte-Carlo simulation-based technique that extracts feature shape information from top-down CD-SEM images, is applied to study advanced process steps of etched polysilicon layers. True bottom CDs and sidewall angles are among the parameters obtained during real-time wafer inspection. Comparison is made to FIB cross-sections obtained independently from select test sites.
The ever decreasing trend in feature geometry has placed increased importance on the concept of obtaining accurate and repeatable shape information at both the photo and etch steps. Traditional CD-SEM measurement algorithms are known to produce highly repeatable results but with large measurement bias depending on the feature shape (bias = average reported measurement - true value). In this paper we show the value of using Critical Shape Metrology (CSM), a physics-based Monte Carlo model, to extract shape information (sidewall angle, top rounding, footing,...) as well as CD measurements with very low bias, without compromising repeatability and throughput. Shape information and CD bias have been quantified through the use of a CD-AFM for all measurements taken using CSM. Several set of data are also compared to different scatterometry tools.
With critical dimensions (CD) of integrated circuits shrinking to tens of nanometers, accurate metrology of three-dimensional feature shapes at different stages of the lithographic process becomes crucial to circuit performance. We propose Critical Shape Metrology (CSM), a CD-SEM-based technique that extracts accurate feature shape information from images obtained during routine in-line wafer inspection. Intensity profiles from CD-SEM images of known materials are compared in real time to profiles in an off-line generated Monte-Carlo SEM simulation library for the same materials with various model shapes. When the best match is found, metrics like bottom CD, top CD, sidewall angle, foot size and angle, and corner rounding can be obtained with high accuracy. The proposed technique takes advantage of the high resolution and throughput of low-voltage CD-SEMs, and does not require any additional tool calibration beyond the standard calibrations performed for conventional top-down CD metrology. While similar to optical scatterometry in concept, this technique allows for measurement of both isolated targets and dense arrays. Examples of performance on etched polysilicon and resist lines of different shapes are included and compared to SEM cross-sections and CD-AFM data.