In this paper, we present a mixed-technology micro-system for electronically manipulating and optically detecting virusscale
particles in fluids that is designed using 3D integrated circuit technology. During the 3D fabrication process, the
top-most chip tier is assembled upside down and the substrate material is removed. This places the polysilicon layer,
which is used to create geometries with the process' minimum feature size, in close proximity to a fluid channel etched
into the top of the stack. By taking advantage of these processing features inherent to "3D chip-stacking" technology,
we create electrode arrays that have a gap spacing of 270 nm. Using 3D CMOS technology also provides the ability to
densely integrate analog and digital control circuitry for the electrodes by using the additional levels of the chip stack.
We show simulations of the system with a physical model of a Kaposi's sarcoma-associated herpes virus, which has a
radius of approximately 125 nm, being dielectrophoretically arranged into striped patterns. We also discuss how these
striped patterns of trapped nanometer scale particles create an effective diffraction grating which can then be sensed with
macro-scale optical techniques.
We present an alternative signaling method for multi-channel fiber ribbon based optical links. The method is based on a hybrid of differential signaling and single-ended channels. Channels are grouped into code blocks of n-bits. Each code word transmitted in the block is restricted to conform to an n choose m rule. Electrical drivers steer current between m active VCSELS with no dummy loads. A virtual reference is synthesized from the received signals and used for differential discrimination. This signaling method approaches the signal-to-noise characteristics of fully differential signaling but can be implemented with significantly lower channel overhead, giving as much as a 33% reduction in fiber count and a 44% reduction in power. Further, code utilization rates on these links can be as low as 51%, leaving substantial code space available for ECC or channel management functions. In this paper, we describe the signaling method and present a prototype transceiver chip. The transceiver is implemented in 0.25um UTSi Silicon-on-Sapphire technology with flip-chip bonded VCSEL and photodetector arrays. The design demonstrates a pin-compatible alternative to the POP4-MSA transceiver standard with 125% greater data throughput and 25% better power efficiency.
This paper describes a new low-power, area-, and pin-efficient alternative to differential encoding for high-performance chip-to-chip and backplane signaling. The technique, called multi-bit-differential-signaling (MBDS), consists of a new design for the driver and link termination network coupled with a novel coding system based on “N choose M (nCm)” codes. In an nCm-coded MBDS channel, there are <i>n</i> physical interconnections over which all code symbols carry exactly <i>m</i> 1-bits. This property gives MBDS links signal-to-noise and transmission characteristics comparable to pair-wise differential links such as low-voltage differential signaling (LVDS). Moreover, MBDS is compatible with commercial LVDS receivers in point-to-point and multi-point bus topologies. However, because MBDS channels have a higher information density, they use up to 45% less power and up to 45% fewer I/O pads than equivalent differentially encoded buses.
Proc. SPIE. 5346, MOEMS and Miniaturized Systems IV
KEYWORDS: Switches, Waveguides, Microopto electromechanical systems, Vertical cavity surface emitting lasers, Chemical elements, Analog electronics, Digital electronics, Signal detection, Systems modeling, Device simulation
Densely integrated systems in the future will incorporate device and communication technologies that span the domains of digital and analog electronics, optics, micro-mechanics, and micro-fluidics. Given the fundamental differences in substrate materials, feature scale and processing requirements between integrated devices in these domains, it is likely that multi-chip, system-in-package, integration solutions will be required for the foreseeable future. The multi-domain nature of these systems necessitates design tools that span multiple energy domains, time and length scales, as well as abstraction levels. This paper describes a case study of the modeling of a photonic/multi-technology system based on a 3D volumetric packaging technology implemented with Fiber Image Guide (FIG) based technology. It is 64x64 fiber crossbar switch implementation using three Silicon-on-Sapphire mixed signal switch die with flip-chip bonded VCSEL and detector arrays. We show a single end-to-end system simulation of the O/E crossbar working across the domains of free-space and guided wave optical propagation, GaAs O/E and E/O devices, analog drivers and receivers and integrated digital control.
In this paper, we present a system-level simulation and analysis of a diffractive optical MEM Grating Light Valve. The simulations are performed in a system-level multi-domain CAD framework developed at the University of Pittsburgh. Including the electrical, mechanical, and optical domains, this framework allows the user to design micro-optical systems by examining performance measures of the entire system. In this paper, we provide a brief background of the models that are used for signal and device simulation, and use these results for the simulation and analysis of the promising GLV device for applications in a projection system.
There are a variety of factors that can limit the set of allowable code words that are useable on an optical memory block. In this paper, we will primarily consider inter- symbol interference (ISI) and the noise margins required to represent an individual bit. Fo example, code words must maintain a specific topological separation of '1' bits so that ISI does not raise the intensity of neighboring '0's' above a pre-set threshold. Typically this is accomplished by a static encoding that uses a pre-selected set of code words based on these properties of the storage media and the optical system. Alternatively, our approach provides for a dynamic analysis of all data currently stored in the region surrounding a particular block and defines the allowable code words uniquely for each block. We assume the existence of a 'smart' read head that is capable of analyzing a page of data and calculating the allowable codes in real-time based on the actual data in the surrounding region. We use point-spread function based mathematical model for optical readout system to evaluate and carry out data encoding. Our experiments show 81% spatial utilization while recent publications present only 45% utilization.
We present a novel design for optoelectronic-multi-chip- modules based small segments of rigid imaging fiber bundles. These packages have very small (chip-scale) geometries and support bandwidth and latency comparable to on-chip interconnections.
Micro-optical-electrical-mechanical systems (MOEMS) present a new set of challenges for systems on a chip (SoC) and mixed- technology designers including the need for mixed-signal multi-domain simulation. We present new modeling techniques for optical and mechanical MEM components and apply these models to the simulations of a MOEMS switch for optical fiber telecommunications applications.
Computer Aided Design (CAD) tools for modeling optical MEM systems must not only model three distinct domains (optical, electrical, and mechanical), these tools must also model the interactions between the signals of these domains. We strive to create system-level models that are applicable for an optical MEM CAD tool using techniques that support accurate results and interactive computation times. This paper discusses our modeling efforts for multi-domain optical MEM systems with the implementation of these models into our CAD framework, Chatoyant. As an example of our mixed-modeling research, we present the simulation and analysis of a 2 X 2 optical cross connect using Chatoyant. The simulations include the dynamic response of a mechanical beam, diffractive optical effects, and the interaction between these domains.
Computer Aided Design (CAD) tools for modeling optical computing systems use a variety of different optical propagation techniques. However, for modeling micro-systems, common optical modeling techniques are not always valid. This paper discusses various optical propagation models for optical micro-systems by examining the requirements imposed by the physical size of the microsystems and the goal of achieving an interactive CAD framework. Based on these constraints, an appropriate optical model is chosen and used in our opto-electro-mechanical CAD tool, Chatoyant, to perform simulations of 2 X 2 micro-optical switch systems.
In this paper, we present a new packaging architecture for chip-level optical interconnections based on imaging fiber bundles. Imaging fiber bundles consist of densely packed arrays of small core fibers such that an object imaged at one end of the bundle is correspondingly imaged on the opposite end. In optical communication applications fiber bundles can be directly coupled to an array of optical sources. Each spot is carried by multiple fibers that in turn can directly illuminate each element in a detector array. Neither end requires any additional optical elements. Thus, imaging fiber bundles are capable of supporting the spatial parallelism of free space interconnects with relaxed alignment and geometry constraints. This paper is focused specifically on multi-chip system designs.
We employ Modified Nodal Matrix representation, piecewise linear modeling of non-linear devices, and piecewise characterization of signals to accomplish the simulation of mixed technology system. Piecewise simulation modeling for both optoelectronic and mechanical devices is used to decrease the computational task and allow for a trade-off between accuracy and speed. The extraction from device level simulation of circuit models, which characterize high level effects in optoelectronic or mechanical devices, allows for the inclusion of these effects into traditional circuit representations for the device. This technique improves the overall simulation accuracy without compromising the efficiency of the simulator. The additional advantage of using the same technique to characterize electrical and mechanical models allows us to easily merge both technologies in complex devices that interact in mixed domains.
To fully exploit the high bandwidth and inherent parallelism of optical memory systems, it is necessary to perform correspondingly parallel computations at or near the interface to the memory system. In this paper, we present a system in which a dynamically reconfigurable processor is built at the optical memory interface. Dynamically reconfigurable processors exploit parallelism at the level of individual machine instructions. They are based on the time multiplexing of gate array logic between various processor configurations, each of which is matched to a particular required computation. This paper is an analysis of the performance of an optically reconfigurable processor in comparison to conventional multiple instruction issue processors. We will show that the volume of configuration data required makes these systems difficult to build in electronic implementations but ideal for implementations with optical memory.
The use of MEMS technology has enabled the fabrication of micro-optical and micro-electro-mechanical systems on a common substrate. This has led to new challenges in computer aided design of optical micro-electro-mechanical systems. We have extended our opto-electronic system DAD tool, Chatoyant, to attempt to meet the needs to optical MEMS designers. This paper present new component models and analysis techniques which extend our tool to support optical MEMS design. We demonstrate these extensions with the analysis of a micro-optical high speed FT engine and a 1 by 2 optical MEM interferometer switch.
This paper describes the implementation of error detection and correction logic in the optoelectronic cache memory prototype at the University of Pittsburgh. In this project, our goal is to integrate a 3-D optical memory directly into the memory hierarchy of a personal computer. As with any optical storage system, error correction is essential to maintaining acceptable system performance. We have implemented a fully pipelined, real time decoder for 60-bit Spectral Reed-Solomon code words. The decoder is implemented in reconfigurable logic, using a single Xilinx 4000-series FPGA per code word and is fully scalable using multiple FPGA's. The current implementation operates at 33 Mhz, and processes two code words in parallel per clock cycle for an aggregate data rate of 4 Gb/s. We present a brief overview of the project and of Spectral Reed-Solomon codes followed by a description of our implementation and performance data.
With the prospect of a "billion transistor" microprocessor chip becoming a reality in the next decade, VLSI photonics will be an important technology for high bandwidth, chip level, I/O. In this paper we describe a system which demonstrates the use of free space optical channels to connect the functional units in a super scalar microprocessor. This approach enables architectures in which the number of functional units available for parallel instruction execution is significantly larger than can be implemented in a purely electronic design. The design is implemented with SEED devices, flip-chip bonded on a O.5prn CMOS silicon chip1 and is currently being fabricated as part ofthe 1997 CMOS-SEED Coop program2. In a super scalar microprocessor, high performance is achieved by executing multiple instructions in parallel. The architecture consists of multiple functional units, each capable of independent execution, with source and result operands delivered via local interconnection busses. During program execution, a control unit works on a buffer filled with instructions that are eligible for execution and selects those instructions that can be executed without a conflict for resources or data. For example, two instructions may be in conflict over a specific functional unit, a bus, or a port to memory or a register file. These types of conflicts are collectively referred to as structural hazards. There may also be a conflict caused by data dependence within a sequence of instructions. In other words, the operand of one instruction depends on the result of another. These are called data hazards. Other conflicts can be caused by uncertainty over the outcome of a conditional branch instruction. In this case it may be unknown whether or not a particular instruction will be executed at all. This is called a control hazard. These conflicts place a limit on the performance of super scalar machine by limiting the number of instructions that can be executed in parallel. In contemporary designs, architects have attempted to circumvent this limit by building additional functional units. This has an obvious impact on structural hazards but can also be effective on data and control hazards when speculative or redundant execution techniques are used3. For example, if a control hazard introduces uncertainty about the outcome of a conditional branch, both execution threads are allowed to proceed until the uncertainty is resolved. At that time, the computation from the untaken branch is simply discarded. Similarly data dependencies can be resolved by speculating as to the result of a dependent computation and discarding an execution thread ifthe guess was wrong. In general, the more speculative instruction execution that is possible, the greater the effective level of instruction parallelism. However, the number of functional units that can be built and connected on a single chip limits electronic designs. As an alternative, we are suggesting a design which implements free space optical channels as the interconnection busses in a multi-chip super scalar system. These high-speed interchip busses allow us to create systems where the number of functional units is significantly larger than can be implemented in a purely electronic design. In this paper we describe a prototype system which implements six integer functional units and three registers files in a three-chip super scalar ALU design. The control unit implements a subset of the MIPS RS-2000 instruction set architecture and is capable of full dynamic (runtime) scheduling ofALU resources. The rest of this paper is organized as follows. We begin with a logical description of the optical bus structure between the chips and the optoelectronic interface. This is followed by a description of the internal organization of the ALU chips. The optical system used to implement the optical interconnect is presented followed by simulation data showing the performance of the optical interconnect. Finally, we give a briefoutline ofour future research.
Recontigurable computing architectures are gaining popularity as replacements for general purpose architectures in many high performance applications. Reconfigurable systems can take advantage of deep computational pipelines, perform concurrent execution and are inherently data flow in nature. Many applications can exploit these systems, such as genomic sequence scanning. Fast Fourier Transform, text searching. and computer vision. Current research efforts are applying reconfigurable computing to perform automatic target recognition, real-time image processing, and hardware implementation of neural networks. However, these architectures suffer from a trade off between slow reconfiguration times versus low logic gate densit'v when used to support large computations. This problem is due to the fact that configuration memory typically resides off-chip and reconfiguration is performed serially. Recent approaches4 solve this problem by adding an on-chip configuration cache that provides faster reconfiguration at the cost of die area. That is, the area overhead of the configuration cache gives a low total logic gate density for the architecture. These disadvantages limit the performance, and therefore the applicability of current reconfigurable systems. In this paper. a reconfigurable processor architecture is proposed that overcomes the limitations discussed above by using high bandwidth optical channels. The optical channels allow fast parallel loading of the reconfiguration control word as well as the migration of the configuration cache off-chip. The migration of configuration cache allows better utilization of the die area for reconfigurable processing elements. Further, it is possible to implement the optical detectors directly in silicon, hich does not require significant alteration of the fabrication processes. These advantages make the optically reconfigurable architecture competitive for high performance applications.
Routing performance of optical interconnection networks is limited by the complexity of switches and the connectivity of the networks. One way to overcome these limitations is to allocate the network bandwidth in a time-division multiplexed (TDM) way. More specifically, an appropriate subset of input-to-output connections can be established during a time slot and all possible connections are established within several time slots. That is, the network is reconfigured with time division multiplexing at an appropriate degree to emulate a fully connected network. Message routing can be done by selecting an appropriate time slot in which the required connection is established. However, the connection latency, which is equal to the multiplexing degree, may be prohibitive in a large network. To reduce the latency, only a subset of all possible connections needs to be established in the network with time-division multiplexing as required by applications. Network reconfiguration with TDM may be done either statically or dynamically. Static reconfiguration can be based on compile time analysis of an application program, while dynamic reconfiguration is controlled at run time. With time- multiplexing, several virtual networks are created in the time domain and the control overhead can be amortized over the number of virtual networks. Simulation studies have been carried out and results show that dynamic reconfiguration with TDM can effectively ease the communication bottlenecks.
We present several optical interconnection structures for multiprocessor applications. In general the communication paradigms used in multiprocessor systems can be classified as either broadcast or or switched point-to-point systems. It has been suggested that it is desirable to additionally support multicasting and simulcasting modes of communication. These modes are not widely implemented in electronics due to the complexity of their implementation. Using a self routing technique called coincident pulse addressing such structures can be realized efficiently in optics. In this paper we address two issues. First we demonstrate that the technique can be implemented with sufficient reliability and scale in technologies which are appropriate for computing applications. Second we discuss the application of these networks to multiprocessor systems. Using linear structures we demonstrate broadcasting multicasting and simulcasting communication networks. By using two dimensional structures we demonstrate multi-port memory access permutation networks and multiple sender versions of the linear networks.
The architecture of Array Processors with Pipelined Busses (APPB) has recently been proposed as a new hybrid optical-electronic parallel computer architecture which uses messagepipelined optical busses for interprocessor communications. In this paper we show how pipelined messages can be interleaved and overlapped so that the communication capacity of a pipelined optical bus is fully utilized. We also show how to align communicating processors in twodimensional APPB so that only one bus cycle is needed for routing messages between any two communicating processors in a given communication structure. Finally a comparison of the cornmunication bandwidth of a pipelined bus with that of an exclusive access bus is given which shows that the pipelined bus achieves an asymptotically linear in number of processors on the bus improvement over the exclusive access bus.