It is suggested that stray-light (SL, also called flare, scattered light) impact can be compensated by modifying standard
OPC method. Compared to traditional optical proximity effect caused by diffraction limit, stray light leads to extremely
long range (~ 100 micrometer ~ 10 millimeter) proximity effect. Appropriate approximation is introduced for stray-light
implemented OPC in such a large scale. This paper also addresses other practical problems in the stray-light OPC and
presents how to solve the problems.
As the k1 factor of lithography process goes lower, model-based optical proximity correction (OPC) has become the most important step of post-tape-out data preparation for critical mask levels. To apply model-based OPC, a lithographic model with optical and resist parameters usually generated by a regression is required. It takes significant turn-around-time (TAT) to obtain the OPC model, normally more than 1 day per mask level. In this paper, we present an automatic and effective OPC model extraction method using the adaptive simulated annealing (ASA) algorithm. By applying this algorithm to extract the optimal model parameter values, we reduced the model parameter fitting time to less than 1 hour. We confirm the reliability and accuracy of the model generated by this method. With this newly developed automatic modeling method, we present a methodology to detect the critical failure on the wafer effectively that can occur by the focus variation during the lithography process. Generally, we sample only one set of measurement CD data taken under a controlled process condition with the best focus. Based on measurement data at the best focus, the in-house lithography simulator, FAITH<sup>TM</sup>, can generate simulated CD data for the multiple defocus levels without measurement data at the variable defocus levels. The multiple defocus models are built based on the simulated CD data and the automatic OPC modeling method makes the model buildings very fast. Finally, through the simulation of OPC result according to the multiple defocus models, we can verify or forecast the defocus effect before realistic patterning on wafers efficiently. We show the capability of weak point detection by this methodology on the 80nm DRAM devices with ArF photolithography.
The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL)  is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.
Current model-based OPC methods are targeting the critical dimension and the fidelity of the design layout. These methods cannot suitably consider the process margin and reveal several problems below 70nm design layout with the low k1 process factor. Although litho-friendly layout methods have been introduced to improve the photolithography process margin, designing perfect litho-friendly layout is difficult because of the designer’s lacking of knowledge about the process and the relationship between the layers. Thus we have developed new OPC methods to increase the process margin for sub-70nm process. In this paper we propose new methods to generate the OPC-friendly layout from the original design by 1) rule-based retargeting, 2) model-based retargeting using NILS values, and 3) model-based retargeting by MEEF values. In addition, we have evaluated the post-processing treatment by NILS or MEEF values after the model-based OPC. The proposed OPC methods are effective for the memory bit line layer and metal layers, which are composed of the complicated 2-dimensional configuration and also have the advantage to compensate the model inaccuracy for the layout having non-periodic pattern structure. While the rule-based retargeting method requires high engineering cost to optimize the retargeting rule, the model-based retargeting method can be easily implemented into the conventional OPC process and do not need the extraction process of the retargeting rule which is not simple for the 2-dimensional patterns. Applying the model-based retargeting we could increase the DOF margin by 50% compared to the normal OPC method for sub-70nm memory device with ArF lithography. It is more effective to use these retargeting methods from the defocused OPC models.
As the lithography process approaches to the low k1 regime, the layout designers are forced to design the litho-friendly layout, which considers the process margin and mask error enhancement factor (MEEF). In addition, the lithography engineers are also impelled to optimize the optical proximity correction (OPC) rules at the full-chip level to eliminate the failures of the printed image on the wafer. Therefore, we have newly developed the simulation-based critical area extraction (CAE) and litho-friendly layout (LFL) design methodology based on the layout editor environment to design the litho-friendly layout and optimize the OPC rules. In this methodology, the critical areas of the full-chip level post-OPC layout, which have the lower process margin and larger critical dimension (CD) variation, are automatically extracted by evaluating the focus-exposure window, normalized image log-slope (NILS) and edge placement error (EPE). The extracted critical areas are sorted according to their causes of failures (i.e., notching, bridging, line-end shortening and larger CD variation, etc.). In order to maximize the process margin and minimize the MEEF at the full-chip level, layout designers and lithography engineers modify the original layout and optimize the OPC rules of the sorted critical areas based on the lithography simulator. The simulator uses the mask decomposition and selective simulation method to reduce the simulation time at the full-chip level. For the convenient CAE, process margin evaluation and layout optimization, the CAE function and lithography simulator are combined with the layout editor environment. Applying this methodology to the memory device of sub-90nm design rule, we have validated that our methodology can capture the pattern failures at the full-chip level and optimize both the original layout and OPC rules of those areas.
Sub-wavelength lithography has made the OPC (Optical Proximity Correction) technology one of the most precious commodities for the fabrication of semiconductor devices. Highly accurate gate CD (Critical Dimension) control and design rule shrinkage have become possible through the development of the OPC technology. Nevertheless, the device specifications require a more accurate gate CD control than the current OPC tools can cope with. For the model-based OPC to meet this tight CD specification, the model calibration process is very important. Current model-based OPC tools use their OPC models which usually cover the full-chip area with one universal model calibrated by comparing the empirical CD with the simulated CD of specially designed test patterns. Despite its safety, a single model for the full-chip OPC is not accurate for 2-dimensional patterns, and does not take into account the long-range effects of the patterning process such as flare noise or macro loading effect which is closely related to pattern density. In this work, we suggest a novel idea that applies the dual model to a single OPC process. We have found out that the CD trends of the patterns in the core and peripheral region of a memory chip differ from each other so that it is difficult to apply the same model for both regions. For the 110nm DRAM devices with 248nm lithography, we can reduce the gate CD variation up to 40% using the dual model OPC compared with the single model OPC. Since the dual model OPC uses two different models for a correction process, it should be carefully applied not to lose the conformity between the empirical process condition and the physical parameters of the models. The proposed dual model calibrated by the conservative modeling process reduces the gate CD variation by 50% compared with the single model OPC for a 90-nm DRAM device with 193nm lithography.
As semiconductor devices are scaled down to the sub-100nm node, the fine control of ACLV (across-chip line-width variation) to improve the performance of chips and the expansion of the process window to enhance yield are required. One of the techniques reducing ACLV is MPPC (model-based process proximity correction). However, it increases pattern complexity and does not guarantee enough process windows. Therefore, we propose a HPPC (hybrid PPC) methodology combining RPPC (rule-based PPC) and MPPC, which correct the gate on active by MPPC for device performance and the field gate by RPPC for process window. In addition, we optimize SRAF (sub-resolution assist feature) design to improve process windows further at the full chip level and apply the multi-step correction, which corrects optical and etch proximity effects separately to minimize ACLV. As the result of the application to the 90nm logic gate, we achieve over 0.3um DOF (depth of focus) and the line-width variation within ±5% of the target CD (critical dimension).
In the exponential drive to go to the smaller feature size, the control of the line width variation becomes more important than ever before. Hybrid PPC (Process Proximity Correction) has been one of the indispensable methods to satisfy the requirements of CD control and yield improvement. In this paper, an effective methodology for hybrid PPC is presented to reduce the data volume and the complexity of patterns and to enhance the accuracy of correction. The selective engine in the hybrid PPC flow classifies the gate patterns into the areas of model-based and rule-based PPC considering a device performance, a modeling accuracy, and the extension of the contact overlap margin. The effective method of edge pattern modeling is exploited to compensate the nonlinear etch proximity effect in the asymmetrical pattern configuration. Using the hybrid PPC method with the 1 nm correction grid, 22% of the additional reduction in the intra-die CD variation compared to the rule-based PPC with 5 nm correction grid has been achieved.
Insufficient metal overlaps over contacts and/or vias impact serious yield loss especially in the borderless-contact- style random logic devices. Vias which are not fully covered by interconnects cause not only the functional error due to the high via resistance but also the reliability problem such as electro migration. It is not sufficient to compensate only optical proximity effects such as line-end shortening and corner rounding for the overlap margin. Since mis-alignment between interconnects and over/underlying features is not negligible even using an advanced alignment system of step and scanner. Therefore, the need for aggressive OPC is increased to cope with the proximity effect and overlay error in metal interconnects. The proposed OPC approach gives a robust metal overlap with fast runtime and allowable data complexity by selective correction for the improperly overlapped contacts and vias. Experimental results for the test design show that the correction time of the metal interconnects takes 11 hours at HP5600 system by applying the proposed correction algorithm.