As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.
As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry’s preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement.
In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.
Recently pattern overlay accuracy becomes more important because of the small pitch patterning. Immersion technology
enabled usage of hyper NA beyond 1.0 and this technology provided a lot of possibility to make a very small patterns.
But there was no significant technical jump for overlay. Therefore chip makers started to compensate non-linear
systematic overlay errors. For example, high order inter-field overlay correction is used to improve overlay performance
between the tool to tool matching. Now chip makers are planning to compensate in-shot(intra-field) overlay with higher
order compensation than before. Scanner vendors provide intra-field matching options such as i-HOPC(intra-field high
order process correction - ASML) and SDM (Super Distortion Matching - Nikon). Those are the methods to match inshot
overlay easily. However there are a lot of arguments what the correct way is to measure the in-shot overlay and how
we can feedback those measured data to APC system. Especially for the distortion measurement of scanner, we have
different data from the mass production trend of distortion.
The pattern dependency and another cause of in-shot (intra-field) overlay error will be defined. This will provide a clue
to solve difference between the mass production in-shot overlay trend and machine distortion data. The final goal of this
study is providing a small hint to design APC system controlling the in-shot(intra-field) overlay with less overlay error.