During the past few years, new technology brought about new problems we face today due to
shrinkage of the feature size. Some of the problems such as Mask Error Enhancement Factor (MEEF), overlay
control, and so on are crucial because large MEEF can make it difficult to satisfy CD target, and bring about
large CD variation. Moreover, it can also lead to degraded CD uniformity which would have an undesired
influence on device properties. Recently, 2-D random contact hole is getting crucial because it normally has
very large MEEF and cause asymmetric proximity effect which can cause large CD variation, and
misalignment of layer-to-layer. In other words, the method of optical proximity correction and building
accurate OPC model for 2-D random contact hole pattern could be key factor obtaining better CD uniformity
with enhanced overlay margin. Furthermore, in order to get very tangible performance, design based
metrology system (DBM) is used to evaluate process performance. Design based metrology systems are able
to extract information of whole chip CD variation. On top of that, OPC abnormality can be identified and
design feedback can be also disclosed.
In this paper, we will investigate novel method for sub 45nm 2-D random contact hole printing.
First, optical proximity effect (OPE) for two dimensional layout will be investigated. Second, the results of
Variable Threshold Modeling (VTM) for various slit contact hole patterns will be analyzed. Third, model
based verification will be done and analyzed through full-chip before creating full-chip mask. Finally, sub
45nm 2-D random contact hole printing performance will be presented by DBM.
As the design rule shrinks to its natural limit, reduction in lithography process margin and high Critical
Dimension (CD) error gives rise to use of many Resolution Enhancement Techniques (RET). Recently, one the popular
RET method to solve the above problem is polarized illumination. It is used to enhance the reduced lithography process
margin and enhance CD uniformity. Polarization lithography basically uses one sided polarized light source. Therefore
process margin increases for smaller design rule patterns. In this paper, we will present the results for polarized
illumination based Optical proximity Correction (OPC) for sub-60nm memory device. First, models for polarization
based and un-polarization based method will be compared for its model accuracy. Second, the process margin
improvement for polarized and un-polarized illumination will be compared and analyzed for poly layer of sub-60nm
memory device. Finally, method for further enhancing CD error within 5% for polarized OPC model will be discussed.
The dawn of the Sub 100nm technology has brought many new exciting challenges for lithography process such as Immersion, OPC, asymmetry illumination, and so on. But, these new technology brought about new problems we face today due to shrinkage of the feature size. Some of the problems such as PR defect, ID bias and Mask Error Factor(MEF) are very important, but the most critical of all for lithography engineer is low process margin created by these technologies.
In this study, we will be presenting the result of the Illumination based assist feature that enhances the lithography process margin for both Exposure Latitude (EL) and Depth Of Focus (DOF), while retaining safety of the scum generation by positioning the assist feature proportional to the illumination for 60nm device. Also, by automatically generating illumination based assist feature on the peripheral region of the mask, we will show that it levels the Critical Dimension (CD) uniformity for pattern of the same dimension located at both cell and peripheral region of the mask. Results will be tested on the mask feature size of 60nm and will be analyzed for both process margin and CD uniformity.
Critical Dimension of gate pattern in CMOS process is the most important parameter for transistor performance and Organic BARC is generally used for controlling gate CD by reducing the substrate reflectivity. After gate etch process, small poly-silicon block defects are formed and those are derived from BARC material. After S/W nitride deposition and etch process the defects become larger and formed block defects of Belly Button type. These “Belly Buttons” are blocking the active area of transistor, make the device characteristic worse and lead to yield loss. To reduce Belly Buttons, we have evaluated various BARC resist filtration methods including new filtration material and smaller size filter in 0.18~0.35 μm CMOS gate pattern process. It was possible to reduce Belly Buttons dramatically using optimized resist filtration method and we finally got the yield up.