Lithography development has become extremely computationally intensive. For a particular technology node
being developed, it is critical to determine the optimum source and OPC/RET for each layer. In this paper we
present a flexible new computation system for automation of source, OPC and RET optimization of advanced lithography layers. Of course, before determining the optimum source/RET/OPC of any layer, it is equally critical to determine the design rules which can be manufactured at a particular technology node. The design rule computational lithography problem is a superset of the source/OPC/RET optimization problem. With an automated methodology, time for process development can be reduced dramatically if a process development engineer can determine the design rules through accurate, automated simulation of the entire flow.
Fabricating defect-free mask blanks remains a major "show-stopper" for adoption of EUV lithography. One
promising approach to alleviate this problem is reticle floorplanning with the goal of minimizing the design
impact of buried defects. In this work, we propose a simulated annealing based gridded floorplanner for single
project reticles that minimizes the design impact of buried defects. Our results show a substantial improvement
in mask yield with this approach. For a 40-defect mask, our approach can improve mask yield from 53% to 94%.
If additional design information is available, it can be exploited for more accurate yield computation and further
improvement in mask yield, up to 99% for a 40-defect mask. These improvements are achieved with a limited
area overhead of 0.03% on the exposure field. Defect-aware floorplanning also reduces sensitivity of mask yield
to defect dimensions.
As the k1 factor of lithography process goes lower, model-based optical proximity correction (OPC) has become the most important step of post-tape-out data preparation for critical mask levels. To apply model-based OPC, a lithographic model with optical and resist parameters usually generated by a regression is required. It takes significant turn-around-time (TAT) to obtain the OPC model, normally more than 1 day per mask level. In this paper, we present an automatic and effective OPC model extraction method using the adaptive simulated annealing (ASA) algorithm. By applying this algorithm to extract the optimal model parameter values, we reduced the model parameter fitting time to less than 1 hour. We confirm the reliability and accuracy of the model generated by this method. With this newly developed automatic modeling method, we present a methodology to detect the critical failure on the wafer effectively that can occur by the focus variation during the lithography process. Generally, we sample only one set of measurement CD data taken under a controlled process condition with the best focus. Based on measurement data at the best focus, the in-house lithography simulator, FAITH<sup>TM</sup>, can generate simulated CD data for the multiple defocus levels without measurement data at the variable defocus levels. The multiple defocus models are built based on the simulated CD data and the automatic OPC modeling method makes the model buildings very fast. Finally, through the simulation of OPC result according to the multiple defocus models, we can verify or forecast the defocus effect before realistic patterning on wafers efficiently. We show the capability of weak point detection by this methodology on the 80nm DRAM devices with ArF photolithography.