MTJ stack is optimized for TMR at low RA region, high PMA and 400oC post annealing
capability. Atomic level smooth bottom electrode with 0.5A roughness was developed and positive effects on
annealing capability and PMA was demonstrated. The scaling challenge of STT-MRAM read operation down
to sub-10nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated
with focus on MRAM cell variation due to advanced lithography patterning techniques. With SADP or DSA,
the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% σ/μ cell area variation, good
enough for sub-10nm technology node.
In this paper we report on the patterning challenges for the integration of Spin-Transfer Torque Magneto-Resistive- Random-Access Memory (STT MRAM). An overview of the different patterning approaches that have been evaluated in the past decade is presented. Plasma based etching, wet echting, but also none subtractive pattering approaches are covered. The paper also reports on the patterning strategies, currently under investigation at imec.