At advanced process nodes, especially at sub-28nm technology, pin accessibility and routability of standard cells has become one of the most challenging design issues due to the limited router tracks and the increased pin density. If this issue can’t be found and resolved during the cell design stage, the pin access problem will be very difficult to be fixed in implementation stage and will make the low efficiency for routing. <p> </p>In this paper, we will introduce a holistic approach for the pin accessibility scoring and routability analysis. For accessibility, the systematic calculator which assigns score for each pin will search the available access points, consider the surrounded router layers, basic design rule and allowed via geometry. Based on the score, the “bad” pins can be found and modified. On pin routability analysis, critical pin points (placing via on this point would lead to failed via insertion) will be searched out for either layout optimization guide or set as OBS for via insertion blocking. By using this pin routability and pin access analysis flow, we are able to improve the library quality and performance.
It is well-known that the available depth of focus (DoF) tend to decrease for each advancing technology node.
Moreover the leveling control on wafer topography has become a challenge to affect the focus control on exposure tool
capability, especially for the critical hole-structure layer of the back end of line (BEoL). In this study, we used the via
layer from the real products as an example of optimizing the exposure tool's leveling system to reduce process-related
influences to improve the intra-field focus control range. First, the focus-exposure matrices (FEMs) were applied to a
wafer in different leveling modes. Then, patterns' critical dimension (CD) in different locations within the same field
were measured to produce the Bossung curves required to determine the best focus. The same steps were repeated on a
bare wafer to illustrate how the process reduced the common depth of focus range. We also introduced the non-optical
leveling sensor, which measured the wafer by the use of physical methods. Since it does not interact with the film stack
or the pattern density, the measurement accuracy will be insensitive to process variation. Therefore, it can be used to
compensate the optically induced errors from the optical leveling system and to expand the useful depth of focus for
improving CD uniformity. Finally, we briefly summarize the improvement ratio achieved of the common DoF using
these optical and non-optical leveling systems with different leveling modes.