The low-frequency noise behavior of nanoscaled fully-depleted silicon-on insulator (SOI) finFETs is investigated and the perspectives of the noise method as a non-destructive diagnostic tool are revealed. The analysis of the (1/f)γ McWhorter noise observed at zero back-gate voltage showed that the trap concentration Not appears to be lower in the case of devices with HfSiON/SiO2 gate dielectric with the uniaxial strain in the inversion channel while the implementation of the HfO2/SiO2 gate stack and the biaxial strain tend to increase the value of Not. The analysis of the back-gate-induced (BGI) and linear kink effect (LKE) Lorentzian noise observed when the back interface is biased in accumulation allowed to estimate the values proportional to equivalent capacitance Ceq. Their front-gate voltage dependencies appear to be different for the devices with HfSiON/SiO2 and HfO2/SiO2 gate dielectric. Also the values proportional to density of the electron-valence-band tunneling currents jEVB were found for the devices studied. The influence of the strain-inducing techniques and gate dielectric type on the values discussed is revealed.
The use of high mobility channel materials such as Ge and III/V compounds for CMOS applications is being explored.
The introduction of these new materials also opens the path towards the introduction of novel device structures which
can be used to lower the supply voltage and reduce the power consumption. The results illustrate the possibilities that are
created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.
In this paper, some new front-back coupling noise effects are described. They have been revealed in partially-depleted SOI MOSFETs under conditions where an accumulating voltage is applied to the back gate. The first effect consists in the appearance of a Lorentzian component in the noise spectra of the front channel current. The time constant for such Lorentzians which are observed in weak and strong inversion decreases with increasing amplitude of the back-gate voltage and is independent of the front-gate voltage. The second effect is the decrease of the amplitude and the turn-over frequency of the LKE noise Lorentzians that are present in the noise spectra due to the EVB tunneling currents. It is shown that the Lorentzians generated under conditions of an accumulating back-gate voltage and the LKE Lorentzians are analogous by their nature. A model is considered whereby the source of the Lorentzians entering the noise spectra in the presence of an accumulating back-gate voltage is the Nyquist noise voltage generated across the p+-n+ junction induced by the back-gate voltage at the source/back gate. The capacitive character of the source-body impedance is the reason for the Lorentzian shape of the noise component generated by those Nyquist fluctuations
As further enhanced functionalities of mobile equipment are predicted, the development of a CMOS technology that provides low-power, high-speed, and low-noise performance has become an urgent and hot issue. For these application driven technologies the complexity must be tackled at different levels to insure the optimisation of the area, the power consumption, the speed and the reliability. Therefore this paper present a review of the solutions implemented at different levels from system down to technology in order to reduce the contribution of the low frequency noise. These achievements are illustrated by experimental results from literature and are inserted in the general context of system design strategies for reducing the 1/f noise contribution.
In a first part dedicated to high-level system and circuit design, we introduce the noise reduction by switching techniques and the methodology for including the noise dispersion in scaled devices for the early design of analogue/RF circuits. In the second part, the 1/f noise is tackled at its origins i.e. the choice of the gate oxide and other critical process steps.