A circuit-topology-driven approach to Optical Proximity Correction (OPC) is presented. By tailoring device
critical dimension (CD) statistical distribution to the device function in the circuit, and ensuring that the CD
distribution stays within the correct (possibly variable) limits during process maturation and other process
changes, it can be an effective tool for optimizing circuit's performance/yield tradeoff in high-volume manufacturing.
Calibre's proprietary Programmable Electrical Rule Checks (PERC) module is used to recognize the
topology. Alternatively, an external static timing tool can be used to identify critical devices.