One of the key challenges in Silicon based optical interconnect system remains to be the efficient coupling of optical signals from the submicron size on-chip waveguides to standard single mode (SM) fibers with low insertion loss (IL) and relaxed alignment tolerance. Large optical alignment tolerance allows optical connectors to be attached to on-chip waveguides passively using standard semiconductor pick-and-place assembly tools that have placement accuracies of 10- 15μm. To facilitate the assembly, optical fiber coupling elements need to be modular and compact. They have to also have low profile to avoid blocking air flow or mechanical interference with other elements of the package. In this paper we report the development of a two-dimensional (2D) SM optical fiber coupling architecture that consists of Si based photonic lightwave circuit (PLC) substrate and a high-density micro-lensed fiber optic connector. The system is compact, efficient and has large optical alignment tolerance. At 1300nm an insertion loss of 2.4dB and 1.5dB was measured for the PLC module and the fiber optic connector, respectively. When the PLC module and connector was aligned together, a total insertion loss of 7.8dB was demonstrated with x,y alignment tolerance of 40μm for 1dB optical loss. The SM optical coupling architecture presented here is scalable, alignment tolerant and has the potential to be manufactured in high volume. To our knowledge, such a system has not been reported in the literature so far.
A major breakthrough to alleviating the interconnect bottleneck in intra cabinet system in HPC may happen by bringing
optics directly to the processor package. In order to do so efficient and compact optical interconnect subassembly
modules that utilize simple optical and electrical interfacing schemes are needed. In our current work the development of
a novel 10-channel, miniature 7mm(W)x1.8mm(L)x3mm(H), optical interconnect transmitter subassembly module is
described. The module consists of a high precision molded optical alignment unit with integrated microlens arrays, highspeed
coplanar waveguide (CPW) electrical interfaces and a VCSEL (Vertical Cavity Surface Emitting Laser) array chip
which is flip chip mounted. The module is designed to uniquely interface vertically with high-speed electrical I/O lines
on a microprocessor style package or a motherboard to convert electrical signals to optical for transmission to other
similar units using a standard (Multi-Terminal) MT style optical connector. We report on optical coupling efficiency,
misalignment tolerance and high-speed electrical and optical measurements of the module. We have measured 40Gb/s
electrical eye for the CPW interfaces on the module and 20Gb/s clear optical eyes for VCSEL assembled module from
all the 10 channels to produce an aggregate transmitter bandwidth of 200Gb/s. We also measured 30Gb/s electrical and
20Gb/s optical eyes for the optical subassembly module that is bonded onto a microprocessor style package substrate.
We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with
Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with
microprocessor package technology and at the same time allow the integration of low cost, high-performance optical
components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser
(VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA)
package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and
Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package.
VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized
45° mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in high-speed
optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as
VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL.
Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully
integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A
fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.
We have proposed and demonstrated the principle of optical decoupling of the AC modulation component in a lossmodulated
Vertical Cavity Surface Emitting Laser (VCSEL) using a detuned duo-cavity device. This approach allows
the VCSEL power to be modulated without changing the photon density in the active region. Analysis of reflectivity
spectra of a Fabri-Perot cavity with absorber shows that at a certain detuning from the resonance wavelength, reflectivity
is almost independent of absorption magnitude. At this spectral detuning between the active region cavity and modulator
cavity, a feedback-free transmission modulation of the VCSEL output is possible. The use a multiple-double-QW
(MDQW) electroabsorption modulator allows absorption swing between 0.2% and 2% per pass. Optical power
modulation of transmission with contrasts up to 40% and chirp of less than 0.05 nm at 930 nm was demonstrated with
our design. Initial cavity resonance detuning is controlled through growth and was determined to be ideally ~0.7 nm
from analysis of stand-alone absorber cavities. Resonance coupling (splitting) was calculated to be less than 0.3 nm in
case of matching resonances. Applying bias at the MDQW modulator section allows adjustment of detuning between
cavities by changing the top cavity resonance wavelength mainly via Kramers-Kronig relations. The high frequency
modulation characteristics can be tuned in this manner to show little or no sign of resonance, in which case the high
frequency roll-off of the modulation response is entirely determined by parasitics of the modulator section. We have
demonstrated a flat (+/-3db) response up to 20 GHz.
We have studied the modulation properties of VCSEL with intracavity multiple quantum well (MQW) electroabsorption
modulator integrated into the top distributed Bragg reflector (DBR) . Small signal analysis of rate equations for loss
modulation shows an intrinsic high-frequency roll-off slope of 1/&ohgr; instead of 1/&ohgr;2 in directly modulated laser diodes, and
consequently bandwidths in excess of 40 GHz are obtainable with this configuration . Possible limiting factors to high
bandwidth were examined by fitting high frequency characteristics to a multi-pole transfer function, and include RC
delay and carrier drift-limited time of flight (TOF) in the modulator intrinsic region. Intracavity loss modulation shows a
strong (+20dB) relaxation oscillation resonant feature in both theory and experiment. As demonstrated, this feature can
be significantly reduced in amplitude using parasitics. We have extracted relative contribution of TOF and parasitic
capacitance by varying the modulator intrinsic region width (105 and 210 nm) and lateral size of the modulator (18 and
12&mgr;m). It was estimated that the small size modulator exhibits parasitics f-3dB at 8GHz. To estimate the carrier TOF
contribution to bandwidth limits, low temperature growth of a 210 nm absorber i-region and MQW was employed to
reduce photogenerated carrier lifetime. Bandwidth limitations were found to be mostly due to diode and metallization
capacitances, in addition to one pole set by the optoelectronic resonance frequency. We have used p-modulation doping
of the gain region to increase the relaxation frequency. Pronounced active Q-switching was observed, yielding pulse
widths of 40 ps at a 4 GHz rate.
We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8Gb/s aggregate data rate).