The growing demand for advanced DRAM technologies requires development of novel process control methodologies reflecting design rule shrinkage. The new challenges for CD SEM metrology of dense feature arrays of DRAM layers are widely considered in the literature and ITRS documents. In addition to traditional SEM metrology methods based on measurement of individual features, the development of novel measurement techniques is required for dense cell arrays at small nodes.[1-3] We considered a novel metrology of CDSEM Critical Dimension (CD) in dense arrays, formed as capacitors in advanced dynamic random-access memory (DRAM) layers. The proposed approach is based on traditional CDSEM metrology methodology with new developments providing flexibility, CD-style high precision, and large statistical sampling capabilities for advanced Statistical Process Control (SPC). The metrology challenge is solved through development of new algorithmic approaches for dense array measurements. The approach was validated on data simulation of extracting geometry (CD) parameters of actual DRAM cell structures and verified on real data.