Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication.
This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35
nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene
interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack
resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A
multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-
2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased
corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical
proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm.
The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the
uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL
test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
Test chip manufacturing is an ongoing program at Selete in order to evaluate all elements of extreme ultraviolet
lithography (EUVL) such as mask, source, exposure tool, flare compensation, resist material, and pattern transfer
processes. One such test chip represents a back end of process - test elements group (BEP-TEG) which is a dual
damascene process with an overlay of 35nm-half pitch (hp). Pattern transfer process development for the BEP-TEG
manufacturing is investigated. The multi-stack films for pattern transfer are coated films only. The main items for
evaluation were resist thickness, necessity of bottom anti-refracting coat (BARC) between resist film and spin on glass
(SOG) film, and the BARC material itself and its thickness. The BARC material was evaluated from the stand points of
outgassing, etching rate, resist pattern collapse, and resist pattern profiles. Working with resultant multi-stack films,
35nm-hp dense line patterns and 70nm-pitch dense contact-hole patterns were successfully transferred to low-k film.
The correlation between the amount and rate of etching and various properties of organic film for multi-layer resist
(MLR) was investigated. The etching critical dimension (CD) of 140-nm pitch interconnects is controlled by the etching
conditions as well as by the properties of the organic film used as the bottom layer resist. Six organic films were tested
that had different densities, hardness values, refractive indexes, and FT-IR peaks. Patterned samples of these films were
exposed using electron projection lithography. The results showed amount of side etching, which effects the etching CD
of interconnects, of the bottom layer depended on the etching rate of the film. In turn, the etching rate depended on a
film's hardness and refractive index, but not on its density. The etching rate decreased with increasing hardness and with
increasing refractive index in the visible wavelength spectrum. Consequently, the etching CD of interconnects can be
better controlled by using an organic film as the bottom layer resist when the film has appropriate properties.
Proc. SPIE. 6151, Emerging Lithographic Technologies X
KEYWORDS: Lithography, Electron beam lithography, Etching, Photomasks, Extreme ultraviolet lithography, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Failure analysis, Back end of line
In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.
Proc. SPIE. 5751, Emerging Lithographic Technologies IX
KEYWORDS: Lithography, Electron beam lithography, Metals, Scanners, Copper, Resistance, Scanning electron microscopy, Transmission electron microscopy, Overlay metrology, Chemical mechanical planarization
We evaluate electron projection lithography (EPL) performance for a via layer at 65-nm and 45-nm technology nodes through the fabrication of a via-chain test element group (TEG) using EPL/ArF mix-and-match (M&M) lithography. The via-chain is prepared by tow-layer metallization using a Cu/low-k single damascene process. Here, Metal 1 (M1) and Metal 2 (M2) are patterned by using an ArF scanner, and Via 1 (V1) is patterned by using an EPL exposure system. For the EPL performance evaluation at 65-nm technology node, we utilized transmission electron microscope (TEM) and confirmed that a 100-nm via-chain is successfully fabricated and a yield of 94% is achieved. For an EPL performance evaluation at 45-nm technology node, also by using TEM, we confirmed that fabrication of a 70-nm via-chain with reasonable quality is feasible although with a lower yield. For our next step we are planning to carry out an EPL performance at 32-nm technology node by printing a via layer and a metal layer using a corresponding via-chain TEG. Here, M1, V1 and M2 will be patterned by using the EPL exposure system. Although an EPL development at 32-nm technology node is still at its early stages, a via-hole resist pattern of 50 nm and a lines and spaces (L/S) resist pattern of 45 nm have almost been completed. These results suggest that EPL is quite promising for meeting the back-end-of-line (BEOL) process requirement for 65-nm, 45-nm and also for 32-nm technology nodes.