Mr. Eiichi Soda Profile

Mr. Eiichi Soda

Researcher at Semiconductor Leading Edge Technologies Inc.

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Publications (6)

PROCEEDINGS ARTICLE | March 23, 2010

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Proc. SPIE. 7636, Extreme Ultraviolet (EUV) Lithography

KEYWORDS: Lithography, Etching, Scanning electron microscopy, Photomasks, Extreme ultraviolet lithography, Optical proximity correction, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | March 23, 2010

Fabrication of 35nm via-hole patterns for interconnect test chips with EUV lithography

Proc. SPIE. 7636, Extreme Ultraviolet (EUV) Lithography

KEYWORDS: Semiconductors, Metals, Error analysis, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, Anisotropy

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PROCEEDINGS ARTICLE | April 1, 2009

Pattern transfer process development for EUVL

Proc. SPIE. 7273, Advances in Resist Materials and Processing Technology XXVI

KEYWORDS: Etching, Silicon, Manufacturing, Scanning electron microscopy, Photomasks, Extreme ultraviolet lithography, Reactive ion etching, Photoresist processing, System on a chip, Overlay metrology

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PROCEEDINGS ARTICLE | April 2, 2007

Correlation between etching and optical properties of organic films for multilayer resist

Proc. SPIE. 6519, Advances in Resist Materials and Processing Technology XXIV

KEYWORDS: Electron beam lithography, Refractive index, FT-IR spectroscopy, Optical properties, Etching, Polymers, Silicon, Scanning electron microscopy, Critical dimension metrology, Semiconducting wafers

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PROCEEDINGS ARTICLE | March 24, 2006

Tri-layer resists process for fabricating 45-nm L&S patterns by EPL

Proc. SPIE. 6151, Emerging Lithographic Technologies X

KEYWORDS: Lithography, Electron beam lithography, Etching, Photomasks, Extreme ultraviolet lithography, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Failure analysis, Back end of line

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In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.

PROCEEDINGS ARTICLE | May 6, 2005

EPL performance in 65-nm node metallization technology and beyond

Proc. SPIE. 5751, Emerging Lithographic Technologies IX

KEYWORDS: Lithography, Electron beam lithography, Metals, Scanners, Copper, Resistance, Scanning electron microscopy, Transmission electron microscopy, Overlay metrology, Chemical mechanical planarization

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