It is anticipated that once silicon switch I/Cs reach 51.2Tbps, there will be a need to migrate from electrical I/Os to optical I/Os. This drives the need to co-package optical engine transceivers with the high-performance silicon switch. In this paper, we explore the challenges, compare the various solutions, and provide guidance from an assembly and optical connector design perspective. Our focus is on single-mode optic solutions privileged for mid to long range optical links. Topics covered include optical interconnect density to the silicon photonics chip, integrated optical interconnects vs pigtail fiber ribbons, socketable vs. μBGA optical engines, laser source location and special requirements for the optical connectors. The ability to embed optics in the first level package is a disruptive capability needed to meet the everincreasing bandwidth demands for data communication. The benefits of such configurations are discussed, as well as the challenges for thermal management and system yields.
Single-mode integrated photonics assembly is challenging due to the tight alignment required for optical connections. To address this, we have developed a parallelized fiber assembly process using self-alignment of fiber arrays in V-grooves defined on the photonic chip. This approach is compatible with standard automated high-throughput pick and place tools, thus improving the scalability and cost-efficiency of photonic packaging. We describe our efforts toward increasing the assembly throughput as well as making the photonic connections compatible with high temperatures from downstream microelectronic assembly processes, such as lead-free solder reflows. The ability to survive these higher temperatures allows the pretesting of optical engines and paves the way for true co-integration of photonics and electronics. We have shown that attaching fibers to chips using multiple adhesives with partitioning of their function provides substantial gains in both throughput and reliability at a relatively small cost of dispense complexity. The fibers are tacked in place with lengthy adhesive cures performed in a batch process outside of the placement tool so as not to impact the placement tool’s throughput. This approach allows for strong long term structural integrity along with optimized optical index matching between the fiber and the waveguide coupler of the photonic dies. Not only did we observe the same peak optical performance that we previously reported, but we have also demonstrated no experimentally significant optical penalty after 5x lead-free solder reflows, in operational temperature between -15°C and 150°C and, after aggressive microelectronic environmental stressing going beyond the parameters traditionally used in optics. The ability to embed single mode optics in the first level package is a disruptive capability contributing to enable the high-density interconnects needed to meet the ever-increasing bandwidth demands for data communication. We discuss the benefits of such configurations, as well as the challenges for thermal management and system yields.
The packaging of photonic devices remains a hindering challenge to the deployment of integrated photonic modules. This is never as true as for silicon photonic modules where the cost efficiency and scalability of chip fabrication in microelectronic production facilities is far ahead of current photonic packaging technology. More often than not, photonic modules are still packaged today with legacy manual processes and high-precision active alignment. Automation of these manual processes can provide gains in yield and scalability. Thus, specialized automated equipment has been developed for photonic packaging, is now commercially available, and is providing an incremental improvement in cost and scalability. However, to bring the cost and scalability of photonic packaging on par with silicon chip fabrication, we feel a more disruptive approach is required. Hence, in recent years, we have developed photonic packaging in standard, highthroughput microelectronic packaging facilities. This approach relies on the concepts already responsible for the attractiveness of silicon photonic chip fabrication: (1) moving complexity from die-level packaging processes to waferlevel planar fabrication, and (2) leveraging the scale of existing microelectronic facilities for photonic fabrication. We have demonstrated such direction with peak coupling performance of 1.3 dB from standard cleaved fiber to chip and 1.1 dB from chip to chip.
The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.