Traditionally, the optical proximity correction (OPC) is to deliver the solution to ensure the nominal after-development-inspection (ADI) contours on target. As the technology node keeps shrinking to 28nm and beyond, the OPC is expected to cover the lithography process window (PW), etch PW, and overlay margin as well. As a result, more and more advanced functions are included in OPC to achieve the awareness of multiple cost functions, such as the nominal EPE, PW effective EPE, the enclosure of above and underneath layers, and so on. These inclusions are at the cost of the run time and complexity of OPC solution. In this paper, we demonstrated a methodology by adopting design rule check (DRC) algorithm in repair flow to fix hot spots. In accordance to OPC verification check, the subsequent DRC movements were applied to those hot spots only. With a straightforward recipe tuning, a fast convergence of OPC can be achieved. The results exhibit the run time improvement without compromising the OPC performance. We further evaluated by real cases the effects of the DRC-based repair algorithm on the error convergence and final repair effects, by comparing to the standard OPC solution.
In the process of optical proximity correction, layout edge or fragment is migrating to proper position in order
to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE can be also
taken into account as a part of cost function for optimal fragment displacement. Several factors are devised in favor of
OPC stability, which can accommodate room for high mask error enhancement factor (MEEF), lack of process window,
catastrophic pattern failure such as pinch/bridge and improper fragmentation. As technology node becomes finer, there
happens conflict between OPC accuracy and stability. Especially for metal layers, OPC has focused on the stability by
loss of accurate OPC results. On this purpose, several techniques have been introduced, which are target smoothing,
process window aware OPC, model-based retargeting and adaptive OPC. By utilizing those techniques, OPC enables
more stabilized patterning, instead of realizing design target exactly on wafer.
Inevitably, post-OPC layouts become more complicated because those techniques invoke additional edge, or
fragments prior to correction or during OPC iteration. As a result, jogs of post OPC layer can be dramatically increased,
which results in huge number of shot count after data fracturing. In other words, there is trade-off relationship between
data complexity and various methods for OPC stability.
In this paper, those relationships have been investigated with respect to several technology nodes. The mask
shot count reduction is achieved by reducing the number of jogs with which EPE difference are within pre-specified
value. The effect of jog smoothing on OPC output - in view of OPC performance and mask data preparation - was
studied quantitatively for respective technology nodes.
In the past several years, DFM (design for manufacturability) is widely used in semiconductor process. DFM is
to make layout design optimized for manufacturability's sake. Lithography friendly design (LFD) is one branch of DFM.
To enhance process margin of photolithography, layout designers typically modify their layout design with the
application of DFM or LFD tools. Despites those application, it is still not enough to realize enough process window as
technology node goes to beyond 45nm. For these reasons, OPC (Optical proximity correction) engineers apply
additional layout treatment prior to applying OPC. That is called as table-driven retarget, which is typically conducted by
rule-based table. Similar to rule-based OPC, table-driven retarget also has limitations in its application.
In this paper, we presented a model-based retargeting method to overcome the limitation of table-driven retarget.
Once the criteria of process window has been set, we let OPC tool simulate the process window of each layout of design
firstly. Then, if the output value of the simulated result cannot meet the preset criteria, OPC tool resizes the layout
dimension automatically. OPC tool will do retarget-OPC-retarget iterations until process windows of all of designs
become within the criteria. After all, the model-based retarget can guarantee accurate retarget and avoid over or under
retarget in order to improve process window of full chip design.