Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit
(PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides
functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is
why printing fidelity is very challenging on photonics patterns.
In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The
first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The
first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool
design and does not need any retargeting step before OPC. We will compare these two flows on various Si-
Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe
that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow
also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also
discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process
window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an
In a previous work, we demonstrated that the current optical proximity correction model assuming the mask pattern to be analogous to the designed data is no longer valid. An extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason, an accurate mask model has been calibrated for a 14-nm logic gate level. A model with a total RMS of 1.38 nm at mask level was obtained. Two-dimensional structures, such as line-end shortening and corner rounding, were well predicted using scanning electron microscopy pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects, and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular.
In a previous work  we demonstrated that current OPC model assuming the mask pattern to be analogous to the designed data is no longer valid. Indeed as depicted in figure 1, an extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason an accurate mask model, for a 14nm logic gate level has been calibrated. A model with a total RMS of 1.38nm at mask level was obtained. 2D structures such as line-end shortening and corner rounding were well predicted using SEM pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular, as depicted in figure 2.
The 14nm node designs is getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. One of the most critical processes is the contact patterning due to the very aggressive design rules and the process window which becomes quickly limited. Despite the large number of RET applied, some hotspot configurations remain challenging. It becomes increasingly challenging to achieve sufficient process windows around the hot spots just using conventional process such as OPC and rule-based SRAF insertion. Although, it might be desirable to apply Inverse Lithography Technique (ILT) on all hot spots to guarantee ideal mask quality. However, because of the high number of hot spots to repair in the design, that solution might be much time consuming in term of OPC and mask processing.
In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.
Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
Starting from the 45nm technology node, systematic defectivity has a significant impact on device yield loss with each new technology node. The effort required to achieve patterning maturity with zero yield detractor is also significantly increasing with technology nodes. Within the manufacturing environment, new in-line wafer inspection methods have been developed to identify device systematic defects, including the process window qualification (PWQ) methodology used to characterize process robustness. Although patterning is characterized with PWQ methodology, some questions remain: How can we demonstrate that the measured process window is large enough to avoid design-based defects which will impact the device yield? Can we monitor the systematic yield loss on nominal wafers? From device test engineering point of view, systematic yield detractors are expected to be identified by Automated Test Pattern Generator (ATPG) test results diagnostics performed after electrical wafer sort (EWS). Test diagnostics can identify failed nets or cells causing systematic yield loss ,. Convergence from device failed nets and cells to failed manufacturing design pattern are usually based on assumptions that should be confirmed by an electrical failure analysis (EFA). However, many EFA investigations are required before the design pattern failures are found, and thus design pattern failure identification was costly in time and resources. With this situation, an opportunity to share knowledge exists between device test engineering and manufacturing environments to help with device yield improvement. This paper presents a new yield diagnostics flow dedicated to correlation of critical design patterns detected within manufacturing environment, with the observed device yield loss. The results obtained with this new flow on a 28nm technology device are described, with the defects of interest and the device yield impact for each design pattern. The EFA done to validate the design pattern to yield correlation are also presented, including physical cross sections. Finally, the application of this new flow for systematic design pattern yield monitoring, compared to classic inline wafer inspection methods, is discussed.
Standard OPC models consist of a physical optical model and an empirical resist model. The resist model compensates the optical model imprecision on top of modeling resist development. The optical model imprecision may result from mask topography effects and real mask information including mask ebeam writing and mask process contributions. For advanced technology nodes, significant progress has been made to model mask topography to improve optical model accuracy. However, mask information is difficult to decorrelate from standard OPC model. Our goal is to establish an accurate mask model through a dedicated calibration exercise. In this paper, we present a flow to calibrate an accurate mask enabling its implementation. The study covers the different effects that should be embedded in the mask model as well as the experiment required to model them.
From 28 nm technology node and below optical proximity correction (OPC) needs to
take into account light scattering effects from prior layers when bottom anti-reflective coating
(BARC) is not used, which is typical for ionic implantation layers. These effects are complex,
especially when multiple sub layers have to be considered: for instance active and poly structures
need to be accounted for.
A new model form has been developed to address this wafer topography during model
calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification
(using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction
and verification. This paper discusses an exploration of this new model results using extended
wafer measurements (including SEM). Current results show good accuracy on various
The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.
Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted
overexposure by wafer topography with technology node downscaling evolution , . Starting from 2xnm technology
nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer
topography which can cause drastic pattern degradation , . This phenomenon is expected to be attenuated by the
use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a
consequence, computational lithography solutions are currently under development in order to correct wafer
topographical effects on mask . For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography
effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer
In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology
is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational
verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC
flow for chip scale mask correction is presented with quality and run time penalty analysis.
From 28nm technology node and below, Optical Proximity Correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for implant layers. In this paper, we implement a sub-layer aware simulation method into a verification tool for Optical Rule Check (ORC) that is used on full 28nm test chip. The sub-layer aware verification can predict defects that are missed by standard ORC. SEM-CD review and defectivity analysis were used to confirm the validity of the sub-layer aware model on wafer.
As EUV Lithography is not ready yet for sub-20nm node manufacturing, ArF immersion lithography must extend its capability. Among various double patterning techniques already explored, Litho-Etch-Litho-Etch (LELE) is one of the main streams considered today to continue scaling at 20nm and below. Our paper presents an application of a new OPC algorithm designed to ensure a successful double patterning process at 20nm node. A novel OPC technique was applied to 20nm contact and M1 layers. It is intended for both double and multi-patterning lithography technologies providing model based capability for concurrent correction of the split layouts ensuring a robust stitching overlap of the cut features and preventing inter-mask bridging. We have also developed an OPC verification methodology for DP failures due to dose, focus, mask and overlay errors. One of the most critical challenges of DP technology is: ensuring sufficient stitching of the cut design shapes and preventing a risk of inter-mask shape bridging. This problem is rapidly exacerbated by the overlay error. It is demonstrated that the new OPC algorithm results in enhanced stitching overlap and a good space control between inter-mask shapes, thus, minimizing DP process implications on circuit reliability.
The low-k1 domain of immersion lithography tends to result in much smaller depths of focus (DoF) compared to prior technology nodes. For 28 nm technology and beyond it is a challenge since (metal) layers have to deal with a wide range of structures. Beside the high variety of features, the reticle induced (mask 3D) effects became non-negligible. These mask 3D effects lead to best focus shift. In order to enhance the overlapping DoF, so called usable DoF (uDoF), alignment of each individual features best focus is required. So means the mitigation of the best focus shift. This study investigates the impact of mask 3D effects and the ability to correct the wavefront in order to extend the uDoF. The generation of the wavefront correction map is possible by using computational lithographic such Tachyon simulations software (from Brion). And inside the scanner the wavefront optimization is feasible by applying a projection lens modulator, FlexWaveTM (by ASML). This study explores both the computational lithography and scanner wavefront correction capabilities. In the first part of this work, simulations are conducted based on the determination and mitigation of best focus shift (coming from mask 3D effects) so as to improve the uDoF. In order to validate the feasibility of best focus shift decrease by wavefront tuning and mitigation results, the wavefront optimization provided correction maps are introduced into a rigorous simulator. Finally these results on best focus shift and uDoF are compared to wafers exposed using FlexWave then measured by scanning electron microscopy (SEM).
Resolution Enhancement Techniques have continuously improved over the last decade, driven by the ever growing constraints of lithography process. Despite the large number of RET applied, some hotspot configurations remain challenging for advanced nodes due to aggressive design rules. Inverse Lithography Technique (ILT) is evaluated here as a substitute to the dense OPC baseline. Indeed ILT has been known for several years for its near-to-ideal mask quality, while also being potentially more time consuming in terms of OPC run and mask processing. We chose to evaluate Mentor Graphics’ ILT engine “pxOPCTM” on both lines and via hotspot configurations. These hotspots were extracted from real 28nm test cases where the dense OPC solution is not satisfactory. For both layer types, the reference OPC consists of a dense OPC engine coupled to rule-based and/or model-based assist generation method. The same CM1 model is used for the reference and the ILT OPC. ILT quality improvement is presented through Optical Rule Check (ORC) results with various adequate detectors. Several mask manufacturing rule constraints (MRC) are considered for the ILT solution and their impact on process ability is checked after mask processing. A hybrid OPC approach allowing localized ILT usage is presented in order to optimize both quality and runtime. A real mask is prepared and fabricated with this method. Finally, results analyzed on silicon are presented to compare localized ILT to reference dense OPC.
Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist . This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning  . For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.
Double patterning using 193nm immersion has been adapted as the solution to enable 2x nm technology nodes until the
arrival of EUV tools. As a result the past few years have seen a huge effort in creating double patterning friendly design
flows. These flows have so far proposed a combination of decomposition rules at cell level and/or at placement level as
well as sophisticated decomposition tools with varying density, design iteration and decomposition complexity penalties.
What is more, designers have to familiarize themselves with double patterning challenges and decomposition tools. In
this paper an alternative approach is presented that allows the development of dense standard cells with minimal impact
on design flow due to double patterning. A real case study is done on 20nm node first metal layer where standard cells
are designed without considering decomposition restrictions. The resulting layout is carefully studied in order to
establish decomposition or color rules that can map the layout into two masks required for double patterning but without
the need of complex coloring algorithms. Since the rules are derived from a decomposition unaware design they do not
in return impose heavy restrictions on the design at the cell or placement level and show substantial density gains
compared to previously proposed methods. Other key advantages are a simplified design flow without complex
decomposition tools that can generate a faster time to market solution all at the same time keeping designers isolated
from the challenges of the double patterning. The derived design rules highlight process development path required for
design driven manufacturing.
Design For Manufacturing (DFM) is becoming essential to ensure good yield for deep sub micron technologies. As
design rules cannot anticipate all manufacturing marginalities resulting from problematic 2D patterns, the latter has to be
addressed at design level through DFM tools.
To deploy DFM strategy on back end levels, STMicroelectronics has implemented a CAD solution for lithographic
hotspots search and repair. This allows the detection and the correction, at the routing step, of hotspots derived from
lithographic simulation after OPC treatment.
The detection of hotspots is based on pattern matching and the repair uses local reroute ability already implemented in
Place and Route (PnR) tools. This solution is packaged in a Fast LFD Kit for 28 nm technology and fully integrated in
PnR platforms. It offers a solution for multi suppliers CAD vendors routed designs. To ensure a litho friendly repair, the
flow integrates a step of local simulation of the rerouted zones.
This paper explains the hotspots identification, their detection through pattern matching and repair in the PnR platform.
Run time, efficiency rate, timing and RC parasitic impacts are also analyzed.
The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop
putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival
of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution
Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design.
These new Computational Lithography applications have become one of the most computationally demanding steps in
the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these
The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning
solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust
28nm node and prepare for 20nm.
These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub
resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print
check, aka LFD, for 28nm P&R.
Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last
decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly
important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon
engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire
field through process windows. LMC is catching and reporting weak lithographic points having small process windows
or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters.
ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can
be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at
different field locations. In this study we compare such across-field LMC verification with a reference LMC without any
scanner specific data.
Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various
across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots
or scanner drifts and compared with wafer measurement.
Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the
impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the
methodology on identified critical hot spots.
The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to
the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve
enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can
be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of
much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which
identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert
the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification.
STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach.
The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach
of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to
achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based
As the OPC scripts become more and more complex for advanced technology nodes, the number of parameters
used to control the convergence increases drastically. This paper does not aim to determine what a "good
convergence criteria" is but rather to review the efficiency of the existing OPC solutions in terms of accuracy
and parameter dependence, to solve simple design layouts. Three different OPC solutions, including a "standard
algorithm", a "local convergence OPC" and a more holistic OPC, are compared on a design containing lines and
line-ends. A cost function is used to determine the quality of the convergence for each type of structure. A map
of convergence (iteration vs OPC Option) will be deduced for each structure.
Source Mask Optimization (SMO) technique is an advanced resolution
enhancement technique with the goal of extending optical lithography
lifetime by enabling low k1 imaging [1,2]. On that purpose, an appropriate
source and mask duo can be optimized for a given design.
SMO can yield freeform sources that can be realized to a good accuracy
with optical systems such as the FlexRay ,. However, it had been
showen that even the smallest modification of the source can impact the
wafer image or the process. Therefore, the pupil has to be qualified, in
order to measure the impact of any source deformation.
In this study we will introduce a new way to qualify the difference
between sources, based on a Zernike polynomial decomposition . Such
a method can have several applications: from quantifying the scanner to
scanner pupil difference, to comparing the source variation depending of
the SMO settings etc. The straighforward Zernike polynomial decomposition
allow us to identify some classic optical issues like coma or lens
The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the
art scanner will be limited to a numerical aperture of 1.35. Thus we cannot "simply" apply a shrink factor from
the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions
in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to
enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is
clearly established that early process for these layers will be performed by double patterning technique coupled
with advanced OPC solutions.
In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS)
and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC
solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure
good process control.
This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored
by the French government.
To print sub 22nm node features, current lithography technology faces some tool limitations. One
possible solution to overcome these problems is to use the double patterning technique (DPT). The
principle of the double patterning technique is pitch splitting where two adjacent features must be
assigned opposite masks (colors) corresponding to different exposures if their pitch is less than a
predefined minimum coloring pitch. However, certain design orientations for which pattern features
separated by more than the minimum coloring pitch cannot be imaged with either of the two exposures.
In these directions, the contrast and the process window are degraded because constructive
interferences between diffractive orders in the pupil plane are not sufficient. The 22nm and 16nm nodes
require the use of very coherent sources that will be generated using SMO (source mask cooptimization).
Such pixelized sources while helpful in improving the contrast for selected
configurations, can lead to degrade it for configurations which have not been counted for during the
SMO process. Therefore, we analyze the diffractive orders interactions in the pupil plane in order to
detect these limited orientations in the design and thus propose a new double patterning decomposition
algorithm to enlarge the process window and the contrast of each mask.
Source Mask Optimization (SMO) technique is an advanced RET with the goal of extending optical lithography lifetime by enabling low k1 imaging [1,2]. Most of the literature concerning SMO has so far focused on PV (process variation) band, MEEF and PW (process window) aspects to judge the performance of the optimization as in traditional OPC . In analogy to MEEF impact for low k1 imaging we investigate the source error impact as SMO sources can have rather complicated forms depending on the degree of freedom allowed during optimization.
For this study we use Tachyon SMO tool on a 22nm metal design test case. A free form and parametric source solutions are obtained using MEEF and PW requirements as main criteria. For each type of source, a source perturbation is introduced to study the impact on lithography performance. Based on the findings we conclude on the choice of freeform or parametric as a source and the importance of source error in the optimization process.
In double patterning technology (DPT), two adjacent features must be assigned opposite colors,
corresponding to different exposures if their pitch is less than a predefined minimum coloring pitch.
However, certain design orientations for which pattern features separated by more than the minimum
coloring pitch cannot be imaged with either of the two exposures. In such cases, there are no aerial
images formed because in these directions there are no constructive interferences between diffractive
orders in the pupil plane. The 22nm and 16nm nodes require the use of pixelized sources that will be
generated using SMO (source mask co-optimization). Such pixelized sources while helpful in
improving the contrast for selected configurations can lead to degraded contrast for configurations
which have not been set during the SMO process. Therefore, we analyze the diffractive orders
interactions in the pupil plane in order to detect limited orientations in the design and thus propose a
decomposition to overcome the problem.
For mature technology nodes, main yield detractor is random defectivity.
Nevertheless, some devices can show higher defectivity than rest of devices. Out of
process accident, design related defect is one of suspected root cause. Also, design-based
defect category is expected to increase as technology node decreases. Determining origin
of these additional systematic defects is not easy as these defects are usually residual for
technologies in production, not always predictable by OPC simulator (ex: void defect in
active STI structure), and at least hidden by random defectivity after in-line wafer
In this paper, an automatic flow to track systematic defects within global
defectivity is presented. This flow starts with a relevant selection of several inspection
defect files for a given device. Then the Design Based Binning (DBB) tool performs a
fine alignment of the whole multi wafer inspection data set with design file. The resulting
aligned defect file is treated by an efficient pattern matching algorithm to generate a
design-based binning (DBB) defect file. The integration of this output defect file into a
Yield Management System (YMS) allows easy defect analysis and statistical correlation to electrical results. An example of design-based defects tracking analysis and their impact on yield of a mature technology node device is presented in this paper.
Double patterning (DP) is one of the main options to print devices with half pitch less than 45nm. The basis of DP is to
decompose a design into two masks. In this work we focus on the decomposition of the contact pattern layer. Contacts
with pitch less than a split pitch are assigned to opposite masks corresponding to different exposures. However, there
exist contact pattern configurations for which features can not be assigned to opposite masks. Such contacts are flagged
as color conflicts. With the help of design of manufacturing (DFM), the contact conflicts can be reduced through
redesign. However, even the state of the art DFM redesign solution will be limited by area constraints and will introduce
delays to the design flow. In this paper, we propose an optical method for contact conflicts treatment. We study the
impact of the split on imaging by comparing inverse lithography technology (ILT), optical proximity correction (OPC)
and source mask co-optimization (SMO) techniques. The ability of these methods to solve some split contacts conflicts
in double patterning are presented.
Optical Proximity Correction (OPC) is used in lithography to increase the achievable resolution and pattern transfer
fidelity for IC manufacturing. Nowadays, immersion lithography scanners are reaching the limits of optical resolution
leading to more and more constraints on OPC models in terms of simulation reliability. The detection of outliers coming
from SEM measurements is key in OPC . Indeed, the model reliability is based in a large part on those measurements
accuracy and reliability as they belong to the set of data used to calibrate the model. Many approaches were developed
for outlier detection by studying the data and their residual errors, using linear or nonlinear regression and standard
deviation as a metric .
In this paper, we will present a statistical approach for detection of outlier measurements. This approach consists of
scanning Critical Dimension (CD) measurements by process conditions using a statistical method based on fuzzy CMean
clustering and the used of a covariant distance for checking aberrant values cluster by cluster. We propose to use
the Mahalanobis distance  in order to improve the discrimination of the outliers when quantifying the similarity within
each cluster of the data set.
This fuzzy classification method was applied on the SEM CD data collected for the Active layer of a 65 nm half pitch
technology. The measurements were acquired through a process window of 25 (dose, defocus) conditions. We were able
to detect automatically 15 potential outliers in a data distribution as large as 1500 different CD measurement. We will
discuss about these results as well as the advantages and drawbacks of this technique as automatic outliers detection for
large data distribution cleaning.
In advanced technology nodes, due to accuracy and computing time constraint, OPC has shifted from discrete simulation
to pixel based simulation. The simulation is grid based and then interpolation occurs between grid points. Even if the
sampling is done below Nyquist rate, interpolation can cause some variations for same polygon placed at different
location in the layout. Any variation is rounded during OPC treatment, because of discrete numbers used in OPC output
file. The end result is inconsistency in post-OPC layout, where the same input polygon will give different outputs,
depending on its position and orientation relative to the grid. This can have a major impact in CD control, in structures
like SRAM for example, where mismatching between gates can cause major issue.
There are some workarounds to minimize this effect, but most of them are post-treatment fix. In this paper, we will try to
identify and solve the root cause of the problem. We will study the relationship between the pixel size and the
consistency of post OPC results. The pixel size is often set based on optical parameters, but it might be possible to
optimize it around this value to avoid inconsistency. One can say that the optimization will highly depend on design and
not be possible for a real layout. As the range of pitch used in a design tends to decrease, thanks to fix pitch layouts, we
may optimize pixel size for a full layout.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
At 45 and 32 nm nodes, one of the most critical layers is the Contact one. Due to the use of hyper NA imaging, the
depth of focus starts to be very limited.
Moreover the OPC is rapidly limited because of the increase of the pattern density. The limited surface in the dark field
region of a Contact layer mask enforces the edges movement to stop very quickly.
The use of SRAF (Sub Resolution Assist Feature) has been widely use for DOF enhancement of line and space layers
since many technology node. Recently, SRAF generated using inverse lithography have shown interesting DOF
improvement1. However, the advantage of the ideal mask generated by inverse lithography is lost when switching to a
manufacturable mask with Manhattan structures. For SRAF placed in rule based as well as Manhattan SRAF generated
after inverse lithography, it is important to know what their behavior is, in term of size and placement.
In this article we propose to study the placement of scatter-trenches assist features for the contact layer. For this we have
performed process window simulation with different SRAF sizes and distance to the main OPC. These results permit us
to establish the trends for size and placement of the SRAF.
Moreover we have also take a look of the advantages of using 8 surrounding SRAF (4 in vertical - horizontal and 4 at
45°) versus 4 surrounding SRAF. Based on these studies we have seen that there is no real gain of increasing the
complexity by adding additional SRAF.
The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.
Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers.
This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process
optimization is done for minimum pitch dense lines.
Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features
(SRAF) to assist the patterning of isolated trenches structures.
Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with
silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement
characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability.
Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF
Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking
a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD
uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical
Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the
maskshop to get a reticle CD metrology trend line.
With this trend line, we can:
- ensure the stability at reticle level of the maskshop processes
- put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any
internal maskshop process change or new maskshop evaluation. Changes that require qualification could
be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for
capability reasons, like a new process (new developer tool for example) introduction.
Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with
these specific OPC structures.
In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three
advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are
- for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S
(Lines & Space) reticles
- for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles
- for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles.
For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored.
To average the metrology errors, the structures are placed twice on the reticle.
The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM
(Design Rule Manual) of the dedicated levels to be monitored.
The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level.
We will give an example of an internal maskshop matching exercise, which could be needed when we switched from
an already qualified 50 KeV tool to a new 50 KeV tool.
The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops.
The last part of the paper will show first results on dedicated OPC structures for the 45nm node.
As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical
Proximity Correction (OPC) models grows due to the lithographer's need to ensure high fidelity in the mask-
to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum
feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored.
Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These
effects can be used to improve model accuracy and to better predict the final process window. In this paper,
the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types.
Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.
Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from:
-Static RAM with very aggressive design rules specially at active, poly and contact
-transistor variability control at the chip level
The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm :
-dipole with polarization and regular layout for active level
-dipole with polarization, regular layout and double patterning to cut the line-end for poly level.
These choices have been made based on the printing performances of a 0.17&mgr;m2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.
The quality of model-based OPC correction depends strongly on how the model is calibrated in order to generate a resist image as close to the desired shapes as possible. As the k1 process factor decreases and design complexity increases, the correction accuracy and the model stability become more important. It is also assumed that the stability of one model can be tested when its response to a small variation in one or several parameters is small. In order to quantify this, the small-variation method has been tested on a variable threshold based model initially optimized for the 65nm node using measurements done with a test pattern mask. This method consists of introducing small variations to one input model parameter and analyzing the induced effects on the simulated edge placement error (EPE). In this paper, we study the impact of small changes in the optical and resist parameters (focus settings, inner and outer partial coherent factors, NA, resist thickness) on the model stability. And then, we quantify the sensitivity of the model towards each parameter shift. We also study the effects of modeling parameters (kernel count, model fitness, optical diameter) on the resulting simulated EPE. This kind of study allows us to detect coverage or process window problems. The process and modeling parameters have been modified one by one. The ranges of variations correspond to those observed during a typical experiment. Then the difference in simulated EPE between the reference model and the modified one has been calculated. Simulations show that the loss in model accuracy is essentially caused by changes in focus, outer sigma and NA and lower values of optical diameter and kernel count. Model results agree well with a production layout.