Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.
Before each wafer exposure, the photo lithography scanner’s alignment system measures alignment marks to correct for placement errors and wafer deformation. To minimize throughput impact, the number of alignment measurements is limited. Usually, the wafer alignment does not correct for intrafield effects. However, after calibration of lens and reticle heating, residual heating effects remain. A set of wafers is exposed with special reticles containing many alignment marks, enabling intra-field alignment. Reticles with a dense alignment layout have been used, with different defined intra-field bias. In addition, overlay simulations are performed with dedicated higher order intra-field overlay models to compensate for wafer-to-wafer and across-wafer heating.
Overlay control for semiconductor devices is getting tighter in recent years. In the past, we may only concern the whether the overlay are in spec or not. However, the spec we concerned was the same for both X and Y directions. To achieve the tighter spec in the future, we may consider the asymmetry specs for X and Y directions separately for some specific layers, such as CONT layer. For example, if the spec of X direction is tighter than Y direction, we can lose the precision of overlay from Y direction to let overlay from X direction more precise. Theoretically, the common overlay models such as HOPC or iHOPC set X and Y directions independently. To reach the goal of loss overly from one direction to preserve the overlay from the other direction, we consider the full map measurement overlay historical data. From these data, we can analyze the data to find which overlay targets are more important to X direction, and we can set these corresponding targets as the new measurement locations. This is one concept of “asymmetry” since the chosen measurement locations can provide more precisely correction for the overlay of specific direction. On the other hand, we use the in spec ratio (ISR) index for all measurement overlay targets on wafer to replace the traditional mean plus 3 sigma (M3S) index, since we have the budgets of both X and Y directions. The in spec ratio is defined as ratio that the residuals of X and Y directions fill the corresponding budgets, simultaneously. Since our goal is to maximize the ISR, the traditional M3S optimization algorithm can be replaced by ISR optimization with different overlay specs. That is the reason we call “asymmetry overlay correction”.
As the process generation migrate to advanced and smaller dimension or pitch, the mask
and resist 3D effects will impact the lithography focus common window severely because of
both individual depth-of-focus (iDOF) range decrease and center mismatch. Furthermore,
some chemical or thermal factors, such as PEB (Post Exposure Bake) also worsen the usable
depth-of-focus (uDOF) performance. So the mismatch of thru-pitch iDOF center should be
considered as a lithography process integration issue, and more complicated to partition the
3D effects induced by optical or chemical factors.
In order to reduce the impact of 3D effects induced by both optical and chemical issues, and
improve iDOF center mismatch, we would like to propose a mask absorber thickness offset
approach, which is directly to compensate the iDOF center bias by adjusting mask absorber
thickness, for iso, semi-iso or dense characteristics in line, space or via patterns to enlarge
common process window, i.e uDOF, which intends to provide similar application as
Flexwave (ASML trademark).
By the way, since mask absorber thickness offset approach is similar to focus tuning or
change on wafer lithography process, it could be acted as the process tuning method of
photoresist (PR) profile optimization locally, PR scum improvement in specific patterns or to
modulate etching bias to meet process integration request.
For mass production consideration, and available material, current att-PSM blank, quartz,
MoSi with chrome layer as hard-mask in reticle process, will be implemented in this
experiment, i.e. chrome will be kept remaining above partial thru-pitch patterns, and act as the
absorber thickness bias in different patterns. And then, from the best focus offset of thru-pitch
patterns, the iDOF center shifts could be directly corrected and to enlarge uDOF by increasing
the overlap of iDOF. Finally, some negative tone development (NTD) result in line patterns will
be demonstrated as well.
As device design rule has been made pattern size shrink, LELE (Litho-Etch- Litho-Etch) process is used in advance pattern process more and more. The CD control is one of the most critical factors for semiconductor manufacturing. However, the numbers of current in-line measurement points are not sufficient for the whole wafer CD monitoring. It’s the goal to increase inline monitor capacity without suffering process cycle time. To generate an innovation pattern to reach the goal is the purpose for the advance pattern process.<p> </p> This paper is going to introduce the detection of CD variation by using overlay metrology in LELE process. The target mark was designed from AIM (Advanced Imaging Metrology) overlay mark. By placing Layer 1 and Layer 2 AIM pattern side by side, CD variation will cause related position changed. And it is able to be detected by overlay tool. On the other hand, overlay shift will not influence this model. It has an advantage over the conventional CD measurement tool. First, the overlay tool throughput is 5~10 times faster than traditional CDSEM and the measurement time is saved. Second, we are able to measure CD and overlay at the same time. Both CD/AA performances are considered and the throughput is also gained.
A novel method on advanced node for IBO (Image Based Overlay) data extraction accuracy is demonstrated in this work, and here some special design in triple-AIM (Advanced Imaging Metrology) is able to realize the approach.<p> </p> Since triple AIM design has 3 locations left for patterning layers insertion, a new design with 2 layers locations, location-A (inner) and location-B (middle), are generated by 1st pattering, i.e. once lithography exposure, and the 2 marks grouping are formed on dielectric through lithography and etching process with a predetermined overlay "zero offset" through original mask layout design, as illustrated in Fig. (1).<p> </p> And then, as following top photo resist layer, assumed location-C (outer), lithography patterning process, PR coating, exposure and development complete, full triple-AIM patterns is generated, and 3 sets of overlay data could be obtained, A to B, C to B, C to A. <p> </p>Through re-calculating the overlay raw data of current (2nd patterning layer) to previous (1st patterning layer) layer by averaging [C to B] and [C to A], then theoretically the data extraction of sites would be more accuracy, since the variation of local marks signal, induced by inline process instability, could be minimized through the raw data averaging procedure. <p> </p>Moreover, from raw data [A to B], an extra monitor function for detections of the inline process variation, marks selection and recipe setting optimization could be obtained, since marks in [A] and [BB] locations are both generated in 1st patterning, and with the target "zero". <p> </p>So if the raw data [A to BB] is bigger or smaller than "zero" in some degree, there should be some process issue or marks condition setting error in triple-AIM design.