In this paper we present the limitations of 3rd order distortion corrections based on standard overlay metrology and propose a new method to quantify and correct the cold-lens aberration fingerprint. As a result of continuous shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, most overlay enhancements were achieved by hardware improvements. However there also is a benefit in the computational approach, and so we looked for solutions for overlay improvements in process variation with computational applications.
Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed
with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to
understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the
lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of
scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology
are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay
marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as
chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer
exposures are presented which investigate various aspects of overlay metrology and validate our simulations.
Scanner matching based on wafer data has proven to be successful in the past years, but its adoption into production has
been hampered by the significant time and cost overhead involved in obtaining large amounts of statistically precise
wafer CD data. In this work, we explore the possibility of optical model based scanner matching that maximizes the use
of scanner metrology and design data and minimizes the reliance on wafer CD metrology.
A case study was conducted to match an ASML ArF immersion scanner to an ArF dry scanner for a 6Xnm technology
node. We used the traditional, resist model based matching method calibrated with extensive wafer CD measurements
and derived a baseline scanner manipulator adjustment recipe. We then compared this baseline scanner-matching recipe
to two other recipes that were obtained from the new, optical model based matching method. In the following sections,
we describe the implementation of both methods, provide their predicted and actual improvements after matching, and
compare the ratio of performance to the workload of the methods. The paper concludes with a set of recommendations
on the relative merits of each method for a variety of use cases.
A top challenge for Photolithographers during a process transfer involving multiple-generation scanners is tool
matching. In a more general sense, the task is to ensure that the wafer printing results in the receiving fab will match or
even exceed those of the originating fab. In this paper we report on two strategies that we developed to perform a photo
process transfer that is tailored to the scanner's capabilities. The first strategy presented describes a method to match the
CD performance of the product features on the transferred scanner. A second strategy is then presented which considers
also the down-stream process tools and seeks to optimize the process for yield. Results presented include: ASML
TWINSCAN<sup>TM</sup> XT:1700i and XT:1900i scanners 1D printing results from a line-space test reticle, parametric sensitivity
calculations for the two scanners on 1D patterns, simulation predictions for a process-optimized scanner-matching
procedure, and final wafer results on 2D production patterns. Effectiveness of the optimization strategies was then