As the semiconductor industry advances to ever-smaller nodes with finer feature sizes and more complex mask designs, reticle quality and reticle defects continue to be a top mask yield risk. The primary reticle defect quality requirement is defined as “no reticle defects causing 10% or larger CD error on wafer”. Beginning at around the 7 nm Logic node, EUV lithography will start pilot production in several leading fabs. EUV masks stress reticle defectivity requirements for mask shops even more than optical masks due to the larger printing impact from a similar size defect on the mask, and the greater cost and longer cycle time for EUV masks. In a mask shop, generally there are three use cases for a blank inspection system, which are used to monitor and improve mask defectivity; 1) Inspecting process monitor masks, which are used to partition the mask process and identify defect excursions, 2) inspecting ‘witness’ blanks, which are used to measure and control defectivity in each process tool / chamber and 3) inspecting incoming mask blanks to ensure defect-free starting materials for advanced optical and EUV reticles. Traditionally, mask shops have been using bright field confocal technology to perform these tasks. However, due to more stringent defect requirements and the flexibility necessary to support these varied use cases, the industry requires a new approach to drive yield improvements in mask manufacturing. In this paper, we report on the introduction of a new system that provides superior sensitivity, with very high throughput and the flexibility to adapt to many different use cases in a production environment.
193nm immersion lithography is the mainstream production technology for the 22nm half pitch (HP) DRAM manufacturing. Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts extreme pressure on the intra-field overlay, to which mask registration error may be a significant error contributor . The International Technology Roadmap for Semiconductors (ITRS ) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 22nm HP node, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error impacts intra-field wafer overlay directly and has a major impact on wafer yield. DRAM makers moved several years ago to 6F2 (figure 1, ) cell design and thus printing tilted lines at 15 or 30 degree. Overlay of contact layer over buried line has to be well controlled.
However, measuring mask registration performance accurately on tilted lines was a challenge. KLA Tencor applied the model-based algorithm to enable the accurate registration measurement of tilted lines on the Poly layer as well as the mask-to-mask overlay to the adjacent contact layers. The metrology solution is discussed and measurement results are provided.