Mr. Erik R. Byers Profile

Erik R. Byers

Sr. Engineer at Micron Technology Inc

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Author

Publications (8)

Proceedings Article | 12 April 2013 Paper

A study on the automation of scanner matching

Yuan He, Alexander Serebryakov, Scott Light, Vivek Jain, Erik Byers, Ronald Goossens, Zhi-Yuan Niu, Peter Engblom, Scott Larson, Bernd Geh, Craig Hickman, Hoyoung Kang

Proceedings Volume 8683, 86830W (2013) https://doi.org/10.1117/12.2014402

KEYWORDS: Scanners, Semiconducting wafers, Critical dimension metrology, Wafer-level optics, Optical lithography, Metrology, Cadmium, Optics manufacturing, Databases, Diffractive optical elements

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Proceedings Article | 4 March 2010 Paper

Simulation-based pattern matching using scanner metrology and design data to reduce reliance on CD metrology

Yuan He, Erik Byers, Scott Light, Danielle Hines, Anton Devilliers, Mike Hyatt, Jianming Zhou, Vinay Nair, Zongchang Yu, Yu Cao, Xu Xie, Wenjin Shao, Rafael Aldana, Ronald Goossens, Chang-Qun Ma, Junwei Lu, Hua-yu Liu, Chris Aquino, Peter Engblom, Tjitte Nooitgedagt, Eric Janda

Proceedings Volume 7640, 764014 (2010) https://doi.org/10.1117/12.848255

KEYWORDS: Scanners, Wafer-level optics, Semiconducting wafers, Metrology, Data modeling, Calibration, Critical dimension metrology, Optics manufacturing, Performance modeling, Optical simulations

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Proceedings Article | 4 March 2010 Paper

Improving aberration control with application specific optimization using computational lithography

Jianming Zhou, Youping Zhang, Peter Engblom, Mike Hyatt, Eric Wu, Martin Snajdr, Anton deVilliers, Yuan He, Craig Hickman, Peng Liu, Dennis de Lang, Bernd Geh, Erik Byers, Scott Light

Proceedings Volume 7640, 76400K (2010) https://doi.org/10.1117/12.846697

KEYWORDS: Semiconducting wafers, Scanners, Computational lithography, Optimization (mathematics), Calibration, Finite element methods, Thermal modeling, Computer simulations, Data modeling, Critical dimension metrology

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Proceedings Article | 24 March 2009 Paper

Novel lithography approach using feed-forward mask-based wafer CDU correction increase fab productivity and yield

Shmoolik Mangan, Erik Byers, Dan Rost, Mike Garrett, Merri Carlson, Craig Hickman, Jo Finders, Paul Luehrmann, Robert Kazinczi, Ingrid Minnaert-Janssen, Frank Duray, Baukje Wisse, Nicole Schoumans, Liesbeth Reijnen, Thomas Theeuwes, Michael Ben-Yishai, Rachel Ren, Ryan Gibson, Lior Shoval, Yaron Cohen, Yair Elblinger, Ilan Englard

Proceedings Volume 7272, 72722B (2009) https://doi.org/10.1117/12.815415

KEYWORDS: Photomasks, Semiconducting wafers, Scanners, Lithography, Inspection, Critical dimension metrology, Yield improvement, Wafer-level optics, Metrology, Imaging systems

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The extension of ArF lithography through reduced k1, immersion and double patterning techniques makes lithography a difficult challenge. Currently, the concept of simple linear flow from design to functional photo-mask is being replaced by a more complex scheme of feedback and feed-forward loops which have become part of a complex computational lithography scheme. One such novel lithography concept, called "holistic lithography", was recently introduced by ASML, as a scheme that makes the lithography process a highly efficient solution for the scaled down geometries. This approach encourages efficient utilization of computational lithography and the use of feed-forward and feed-back critical dimension (CD) and overlay correction loops. As sub-nanometer feature dimensions are reached for 3x nodes, with k1 reaching the optics limitations, Mask error enhancement factor (MEEF) values grow fast, thus making mask uniformity fingerprint and degradation throughout its life time a significant factor in printed CDU on the wafer. Whereas the consensus is on the need for growing density of intra-field data, traditional critical dimension scanning electron microscope (CDSEM) Feed backward loops to the litho-cell become unsuitable due to the high density CD measurement requirements. Earlier publications proposed implementing the core of the holistic lithography concept by combining two technologies: Applied Material's IntenCD^TM and ASML DoseMapper . IntenCD metrology data is streamed in a feedforward fashion through DoseMapper and into the scanner, to create a dose compensation recipe which improves the overall CDU performance. It has been demonstrated that the IntenCD maps can be used to efficiently reduce intra-field printed CDU on printed wafers. In this paper we study the integration concept of IntenCD and DoseMapper in a production environment. We implement the feed-forward concept by feeding IntenCD inspection data into DoseMapper that is connected to ASML's TWSINCAN^TM XT:1900i scanner. We apply this concept on printed wafers and demonstrate significant reduction in intra-field CDU. This concept can effectively replace the feedback concept using send-ahead wafers and extensive CDSEM measurements. The result is a significant cost saving and fab productivity improvement. By routinely monitoring mask-based CDU, we propose that all photo-induced transmission degradation effects can be compensated through the same mechanism. The result would be longer intervals between cleans, improved mask lifetime, and better end of line device yield.

Proceedings Article | 16 March 2009 Paper

Process transfer strategies between ASML immersion scanners

Yuan He, Peter Engblom, Jianming Zhou, Eric Janda, Anton Devilliers, Bernd Geh, Erik Byers, Jasper Menger, Steve Hansen, Mircea Dusa

Proceedings Volume 7274, 72742P (2009) https://doi.org/10.1117/12.816417

KEYWORDS: Scanners, Printing, Semiconducting wafers, Reticles, Calibration, Metrology, Scatterometry, Data modeling, Cadmium, Scanning electron microscopy

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Proceedings Article | 26 March 2008 Paper

Characterization of array CD uniformity with respect to pattern density in 193nm dry photolithography

Vishal Sipani, David Kewley, Kaveri Jain, Erik Byers, Bruce Daybell, Anthony Krauth

Proceedings Volume 6923, 69233O (2008) https://doi.org/10.1117/12.773316

KEYWORDS: Reticles, Photoresist materials, Critical dimension metrology, Optical lithography, Photoresist processing, Fluorine, Semiconducting wafers, Polymers, Molecules, Diffusion

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Proceedings Article | 26 March 2007 Paper

Process margin improvement using custom transmission EAPSM reticles

J. Buntin, S. Agarwal, B. Rolfson, R. Housley, B. Baggenstoss, E. Byers, C. Progler

Proceedings Volume 6520, 65202D (2007) https://doi.org/10.1117/12.712368

KEYWORDS: Reticles, Resolution enhancement technologies, Image transmission, Nano opto mechanical systems, Semiconducting wafers, Image processing, 193nm lithography, Etching, Lithography, Databases

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Proceedings Article | 17 May 2005 Paper

Etch, reticle, and track CD fingerprint corrections with local dose compensation

Hans van der Laan, Rene Carpaij, Jouke Krist, Oscar Noordman, Youri van Dommelen, Jan van Schoot, Frans Blok, Christian van Os, Sander Stegeman, Tom Hoogenboom, Craig Hickman, Erik Byers, Troy Gugel

Proceedings Volume 5755, (2005) https://doi.org/10.1117/12.602129

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Reticles, Etching, Scanners, Manufacturing, Actuators, Feedback control, Data modeling, Feedback loops

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Showing 5 of 8 publications

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