Time-to-digital converter (TDC) is a major component for the measurement of time intervals. Recent developments in field-programmable gate array (FPGA) have enabled the opportunity to implement high performance TDC which previously was only possible in dedicated hardware. We propose a TDC with cascaded carry chains, a customized encoder, a highly efficient histogram generator. It’s implemented on a 16nm FPGA while utilizing a Gigabit Ethernet for data transmission. Comparisons with previous works show the proposed TDC has lower resource utilization whilst achieving a better raw linearity which enables the path to high performance multichannel TDCs in demanding time-of-flight (ToF) imaging application.