One of the challenges of scaling Shallow Trench Isolation (STI) is controlling the Vt and Idsat of narrow devices. In this paper, we show that Idsat of narrow devices is strongly affected by changes in mobility due to stress from the trench edge. We also show that Vt and leakage of narrow devices is controlled by dopant re-distribution in the channel caused by TED and boron segregation to the trench sidewalls.
For sub 0.25 micron CMOS processes, Shallow Trench Isolation (STI) is required because of its planarity, high packing density and low junction edge capacitance. After trench etch in the STI process, the top corner of the trench must be rounded in order to achieve stable device performance, reduce inverse narrow width effects and maintain good gate oxide integrity. Several methods of round in the trench corners have been proposed. A post-CMP oxidation step to round the top corner trench has been shown to consume too much of the silicon active area and may not be suitable for sub-0.18micrometers technologies. Furthermore, the post-CMP oxidation can generate a lot of stress even at high temperatures. It has been shown that a 50 nm radius of curvature provides stable device data and a good gate oxide integrity with minimum consumption of the active area. In this paper, we have shown that this radius can be achieved with minimal stress generation using a properly optimized rapid thermal oxidation before oxide fill. Through both 2D oxidation modeling and experimental verification we have shown that an optimum oxidation temperature can be found when coupled with an undercut of the buffer oxide under the silicon nitride mask. Temperature is the primary parameter for rounding of the top corner during oxidation while undercut of the buffer oxide lowers the minimum temperature for a given rounding. A 50 nm radius of curvature can be achieved by the balance of the two parameters. This radius of curvature has been shown to suitable for 0.15 micron technology and beyond.
Control of boron penetration in surface-channel PMOS devices is critical in order to ensure tight threshold voltage (V<SUB>t</SUB>) distribution. Previous work has focused on studying relatively gross boron-penetration effects, which give rise to large shifts in V<SUB>t</SUB>. In practice, low-voltage CMOS technologies are sensitive to small degradation in PMOS V<SUB>t</SUB> scatter due to the onset of boron penetration. Moreover, the use of rapid thermal annealing can give rise to difficult trade-offs between poly depletion and boron penetration. As both of these effects can influence the PMOS V<SUB>t</SUB> we propose a sensitive, systematic, methodology to distinguish between depletion and penetration effects and illustrate its application in a number of advanced CMOS processes, with oxide thickness ranging from 30-50 angstrom.
An integrated shallow trench isolation process utilizing HDP (High Density Plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 micrometer technologies.