The read performance of a spin-transfer torque magnetic random-access memory device is based on the tunnel magnetoresistance of the magnetic tunnel junction cell, which is a function of the resistance values at low and high resistance states of the magnetic layers. To ensure a robust tunnel magnetoresistance value and high yield, magnetic tunnel junction pillar patterning process should have a good local critical dimension uniformity. In this paper, we screen several patterning techniques, such as dry development rinse material-based tone reversal besides the standard patterning, as well as different resists and underlayer materials to improve the local critical dimension uniformity at 50nm pitch extreme ultraviolet pillar printing. The results of the best litho process obtained show an improvement above 20% for the local critical dimension uniformity performance. The performance metrics such as the process windows analysis, pillar circularity and the critical dimension uniformity have also been checked for the promising litho process options. Moreover, the transfer of the post-litho improvements to the etch process have been checked and qualified after several layers of hardmask etch.
Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI
KEYWORDS: Oxides, Metrology, Logic, Statistical analysis, Etching, Germanium, Resistance, Scanning electron microscopy, 3D metrology, Process control, Critical dimension metrology, Algorithm development, Overlay metrology, Standards development, Back end of line
The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.
A methodology to evaluate the memory cell property of STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory) with a CD-SEM (Critical Dimension-Scanning Electron Microscope) was proposed. STTMRAM is one of the promising candidates among various emerging memories, owing to its low power consumption, low latency, and excellent endurance. Meanwhile, the major issues of STT-MRAM are its small resistance window and the etching-induced damage during memory pillar formation process. The resistance variability and the damage region should be minimized to achieve the reliable operation and the size scaling. The correlation analysis between the resistance and the physical dimension was performed. It provided quantitative information required for process development and control, such as the size-independent resistance variability, the width of the damaged region, and the origin of the short failures. They are essential for the investigation of the causes for the cell-to-cell resistance variability as well as for the quantification of the damage during etching process.