Improved lithography resolution provided by EUVL simplifies the patterning process and makes it possible to use less restrictive design rules. This in turn enables cost effective scaling with extendibility. There are several technical challenges and infrastructure gaps that need to be resolved to make EUVL suitable for high volume manufacturing (HVM). These gaps relate to development of a stable and reliable high power EUV source, EUV resist and EUV compatible photomask infrastructure. Realization of Actinic patterned mask inspection (APMI) capability is a critical component of the required Photomask infrastructure [1,2]. Most critical enabler of actinic patterned mask inspection technology/capability has been the EUV source. In this contribution, we will discuss key aspects of the developed High-Volume Manufacturing (HVM) worthy LPD EUV source for APMI. These include performance aspects such as brightness and spatial position stability of the EUV emission, dynamics of the EUV-emitting plasma and long-term stability of the source
With the persistent drive to enable EUV lithography (EUVL) for the continuation of pattern scaling and the close collaborations between suppliers and customers, tremendous progress has been made in the last five years in EUV mask infrastructure development. With the advent of actinic pattern mask inspection (APMI) tool, the only remaining EUV mask infrastructure gap until recently has been closed. We will present real-case examples from inspection of 7nm and 5nm logic node EUV masks with APMI in operation at Intel mask shop and demonstrate that actinic inspection provides defect detection capability beyond the traditional DUV optical and e-beam mask inspection (EBMI) tools for defect control and the guaranty of mask quality. In addition to the main focus on APMI and through-pellicle inspection in this paper, we also provide a brief discussion of other key EUV infrastructure modules for mask production in current EUVL at 0.33NA and future technology extension to enable high NA EUVL at 0.55NA.
Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next
generation technology from development into production. High volume production in mask shops and wafer fabs
demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast
turnaround of reticle repair and defect disposition (W. Chou et al 2007).
Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution
inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution
mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the
mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI
can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically,
minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to
defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane.
This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced
reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results
from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all
the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI
are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between
WPI and AIMSTM.
Deep ultraviolet (DUV) femtosecond-pulsed laser ablation has numerous highly desirable properties for subtractive photomask defect repair. These qualities include high removal rates, resolution better than the focused spot size, minimized redeposition of the ablated material (rollup and splatter), and a negligible heat affected zone. The optical properties of the photomask result in a broad repair process window because the absorber film (whether Cr or MoSi) and the transmissive substrate allow for a high degree of material removal selectivity. Repair results and process parameters from such a system are examined in light of theoretical considerations. In addition, the practical aspects of the operation of this system in a production mask house environment are reviewed from the standpoint of repair quality, capability, availability, and throughput. Focus is given to the benefit received by the mask shop, and to the technical performance of the system.
Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intel's APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.
This article presents the evolution of the first fully automated simulation based mask defect dispositioning and defect management system used since late 2002 in a production environment at Intel Mask Operation (IMO). Given that inspection tools flag defects which may or may not have any lithographic significance, it makes sense to repair only those defects that resolve on the wafer. The system described here is a fully automated defect dispositioning system, where the lithographic impact of a defect is determined through computer simulation of the mask level image. From the simulated aerial images, combined with image processing techniques, the system can automatically determine the actual critical dimension (CD) impact (in nanometers). Then, using the product specification as a criteria, can pass or fail the defect. Furthermore, this system allows engineers and technicians in the factory to track defects as they are repaired, compare defects at various inspection steps and annotate repair history. Trends such as yield and defect commonality can also be determined. The article concludes with performance results, indicating the speed and accuracy of the system, as well as the savings in the number of defects needing repair.
Mask quality is a prime concern to the Intel Mask Operation (IMO) and the Intel wafer fabrication customers. Extreme concern is taken to inspect and repair all defects before shipment. Given that the classification and repair of defects detected by inspection systems is labor intensive, the procedure is prone to human error. Futhermore, since operators manually disposition hundreds of defects each day, it is virtually impossible to eliminate all misclassifications. Due to diffraction effects, not all defects resolve on a wafer. Hence, a defect that an operator may classify as 'real' may indeed be 'lithographically insignifincant'. Conversely an operator may miss a defect that prints, causing a serious reduction in product yield. The DIVAS (Defect, Inspection, Viewing, Archiving and Simulation) system has been described previously and was developed to address these manual classification issues. This paper outlines the fully automated system deployed in a production environment.