The choice of a staggered or coplanar geometry for organic thin-film transistors (TFT) has significant effects on the static and dynamic electronic properties of the transistors. Using two-port network analysis, we find that the parasitic capacitances and thus the unity current-gain (transit) frequencies are significantly more dependent on the gate-to-source overlap in the staggered TFTs than in coplanar TFTs, and that the transit frequency is higher overall when a coplanar geometry is implemented. We show that these differences are primarily attributed to the lower contact resistance in the coplanar TFTs (10 Ohm-cm) as well as smaller parasitic capacitances associated with the gate-to-contact overlaps.
The aim of this work is to fabricate patterned nitride membranes with Si-MEMS-technology as a platform to build up new membrane-electrode-assemblies (MEA) for alkaline fuel cell applications. Two 6-inch wafer processes based on chemical vapor deposition (CVD) were developed for the fabrication of separated nitride membranes with a nitride thickness up to 1 μm. The mechanical stability of the perforated nitride membrane has been adjusted in both processes either by embedding of subsequent ion implantation step or by optimizing the deposition process parameters. A nearly 100% yield of separated membranes of each deposition process was achieved with layer thickness from 150 nm to 1 μm and micro-channel pattern width of 1μm at a pitch of 3 μm. The process for membrane coating with electrolyte materials could be verified to build up MEA. Uniform membrane coating with channel filling was achieved after the optimization of speed controlled dip-coating method and the selection of dimethylsulfoxide (DMSO) as electrolyte solvent. Finally, silver as conductive material was defined for printing a conductive layer onto the MEA by Ink-Technology. With the established IR-thermography setup, characterizations of MEAs in terms of catalytic conversion were performed successfully. The results of this work show promise for build up a platform on wafer-level for high throughput experiments.
We present the technology steps to integrate an Echelle grating in the process flow of silicon-organic hybrid (SOH) modulators or related active devices. The CMOS-compatible process flow on SOI substrates uses a mix of optical i-line lithography and electron beam lithography (EBL). High speed optical data communication depends on wavelength divisions multiplexing and de-multiplexing devices like Echelle gratings. The minimum feature sizes vary from device to device and reach down to 60 nm inside a modulator, while the total area of a single Echelle grating is up to several mm2 of unprocessed silicon. Resist patterning using a variable shape beam electron beam pattern generator allows high resolution. An oxide hard mask is deposited, patterns are structured threefold by EBL and are later transferred to the silicon. We demonstrate a 9-channel multiplexer featuring a 2 dB on-chip loss and an adjacent channel crosstalk better than -22 dB. Additionally a 45-channel Echelle multiplexer is presented with 5 dB on chip loss and a channel crosstalk better than -12 dB. The devices cover an on-chip area of only 0.08 mm2 and 0.5 mm2 with a wavelength spacing of 10.5 nm and 2.0 nm, respectively.
A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.
Organic electronics are gaining increasing interest and attention in electronic device fabrication due to cost advantages
and low process manufacturing temperatures, which allow the use of mechanically-flexible polymeric substrates.
Different patterning techniques for Organic Thin Film Transistors (OTFT) with sub μm channel length are currently
under investigation like inkjet-printing, nanoimprint, optical- and e-beam lithography. This paper describes a new
approach for OTFT fabrication by device patterning with Si stencil lithography. This high resolution shadow mask
technique allows the parallel patterning of sub μm features without the use of photosensitive resists or chemical solvents,
which could lead to a degradation of the sensitive organic semiconductor layer. At first the device pattern is etched into a
thin Si membrane layer, creating design-specific sub μm features. Subsequent this stencil mask is aligned and clamped to
the substrate and material is deposited through the stencil apertures forming the desired device pattern onto the substrate.
By repeating this sequence with different deposition materials a classical top contact TFT architecture with a gate
electrode, gate dielectric, organic semiconductor and source drain contacts can be achieved.
Multi-beam lithography is considered a promising fabrication technology for future node mask making. Due to rising
design complexity and therefore increasing pattern writing times the multi-beam approach has distinguished throughput
advantages compared to state of the art variable shaped beam pattern generators.
A key component of a projection multi-beam writing tool is the programmable blanking-plate for generating the desired
pattern geometry on the mask substrate.
In our case a highly parallel charged particle beam illuminates a Si aperture-plate which shapes and generates many
thousand individual spot beams. These beams pass through a blanking-plate with integrated CMOS electronics for demultiplexing
the writing data. The blanking-plate is equipped with blanking and ground electrodes placed around the
apertures switching the beams "on" or "off", dependent on the desired pattern. The beam array is demagnified by a 200x
reduction optics and the exposure of the mask substrate is done in stripes by a continuous moving stage [1,2].
Cross talk between adjacent beams in the blanking-plate has to be avoided to ensure adequate pattern fidelity and line
edge roughness on the mask substrate. One solution is the insertion of a 3D Si aperture-plate in proximity to the
blanking- plate shielding the blanking electrodes from each other during operation.
We developed and characterized a new process flow for the fabrication of these 3D Si aperture-plates for the case of 43
thousand beams in parallel and will present and discuss the cross talk results for blanking-plates combined with standard
2D and new 3D Si aperture-plates.
A detailed evaluation study has been performed with respect to the suitability of projection electron and ion multi-beam
lithography for the fabrication of leading-edge complex masks. The study includes recent results as obtained with
electron and ion multi-beam proof-of-concept systems with 200x reduction projection optics where patterns are
generated on substrates using a programmable aperture plate system (APS) with integrated CMOS electronics,
generating several thousands of well defined beams in parallel. A comparison of electron and ion projection multi-beam
writing is provided, in particular with respect to the suitability to expose non-chemically amplified resist (non-CAR)
materials. The extendibility of projection multi-beam technologies for 16nm hp, 11nm hp and 8nm hp mask nodes is
discussed as well as for wafer direct write for 22nm hp and below.
KEYWORDS: Semiconducting wafers, Lithography, Electron beams, Electrodes, Prototyping, Electron beam lithography, Electron beam direct write lithography, Silicon, Optical alignment, Photomasks
Projection Mask-Less Lithography (PML2) is a potentially cost-effective multi electron-beam
solution for the 22 nm half-pitch node and beyond. PML2 is targeted on using hundreds of
thousands of individually addressable electron-beams working in parallel, thereby pushing
the potential throughput into the wafers per hour regime. With resolution potential of < 10
nm, PML2 is designed to meet the requirements of several upcoming tool generations.
Two main challenges of future mask making are the decreasing throughput of the pattern generators and the insufficient
line edge roughness of the resist structures. The increasing design complexity with smaller feature sizes combined with
additional pattern elements of the Optical Proximity Correction generates huge data volumes which reduce
correspondingly the throughput of conventional single e-beam pattern generators. On the other hand the achievable line
edge roughness when using sensitive chemically amplified resists does not fulfill the future requirements. The
application of less sensitive resists may provide an improved roughness, however on account of throughput, as well. To
overcome this challenge a proton multi-beam pattern generator is developed [1]. Starting with a highly parallel broad
beam, an aperture-plate is used to generate thousands of separate spot beams. These beams pass through a blanking-plate
unit, based on a CMOS device for de-multiplexing the writing data and equipped with electrodes placed around the
apertures switching the beams "on" or "off", dependent on the desired pattern. The beam array is demagnified by a 200x
reduction optics and the exposure of the entire substrate is done by a continuous moving stage.
One major challenge is the fabrication of the required high aspect deflection electrodes and their connection to the
CMOS device. One approach is to combine a post-processed CMOS chip with a MEMS component containing the
deflection electrodes and to realize the electrical connection of both by vertical integration techniques. For the evaluation
and assessment of this considered scheme and fabrication technique, a proof-of-concept deflection unit has been realized
and tested. Our design is based on the generation of the deflection electrodes in a silicon membrane by etching trenches
and oxide filling afterwards. In a 5mm x 5mm area 43,000 apertures with the corresponding electrodes have been
structured and wired individually or in groups with aluminum lines. The aperture-plate for shaping the beams has been
aligned and mounted on top of the blanking-plate. Afterwards this sandwich has been fixed on a base-plate with a pin
plug as interface. The electrical connection has been performed with a standard chip bonding process to the aluminum
pads on the blanking-plate. Finally, the proof-of-concept deflection unit was evaluated in a test bench. The results of
electrical- and exposure tests are presented and discussed in detail.
With the willingness of the semiconductor industry to push manufacturing costs down, the mask
less lithography solution represents a promising option to deal with the cost and complexity concerns
about the optical lithography solution. Though a real interest, the development of multi beam tools still
remains in laboratory environment. In the frame of the seventh European Framework Program (FP7), a
new project, MAGIC, started January 1st 2008 with the objective to strengthen the development of the
mask less technology. The aim of the program is to develop multi beam systems from MAPPER and
IMS nanofabrication technologies and the associated infrastructure for the future tool usage. This paper
draws the present status of multi beam lithography and details the content and the objectives of the
MAGIC project.
Projection Mask-Less Lithography (PML2) is a potentially cost-effective multi electron-beam solution for the 32nm-node
and beyond. PML2 is targeted on using hundreds of thousands of individually addressable electron-beams working
in parallel, thereby pushing the potential throughput into the wafers per hour regime. With resolution limits <10nm,
PML2 is designed to meet the requirements of several upcoming tool generations.
A PML2 proof-of-concept setup was realized within the framework of the European RIMANA project. It contains all
crucial components of a full-fledged PML2 tool and unambiguously demonstrates the operability of multi electron-beam
projection optics with 200x reduction. In the PML2 proof-of-concept system more than 2000 switchable beams are
generated by a programmable aperture plate system (APS) and projected onto wafer level with 200x demagnification.
Current density (~2 A/cm2) and total current (~10 pA) of each beam are the same as in future PML2 tools, resulting in a
calculated base resolution below 10nm. The PML2 proof-of-concept column has been successfully tested using
resolution templates, verifying 200x reduction and the predicted 22nm hp resolution capability. Furthermore, first
custom designed 32nm hp structures were printed into resist coated Si wafers using an APS test-unit.
Based on the inputs obtained by the PML2 proof-of-concept system and detailed electron-optical calculations, a fully
industry-compatible PML2 Alpha-tool will be realized within the European MAGIC project. Together with the
infrastructure developed within MAGIC, this PML2 Alpha-tool promises to herald the introduction of mask-less
lithography into the industrial environment.
Line edge roughness (LER) and substrate resist interaction of chemically amplified resists (CAR) might be limitations for future mask making. An alternative solution could be the direct patterning of a thin hard mask on top of an absorber using a multiple ion beam pattern generator. Goal of this work was to assess a resistless hard mask structuring by direct patterning and a subsequent transfer into chrome by a dry etch process. Hard mask structuring has been done on the IMS Nanofabrication proof of concept tool which is designed for 40,000 multi-beam operations. For comparison to the resistless approach, a resist based stack patterning has been set up. Hard mask opening and subsequent chrome etching have been accomplished in a state of the art mask etcher. The assessment of both process schemes has been done in terms of feature profile and resolution capability. Finally, throughput estimation for a future production tool, operating with precursor gases and 1.000.000 ion beams has been calculated.
Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. Different absorber layers and manufacturing concepts have been published for the fabrication of reflective EUVL masks. A mandatory step in the EUVL mask making is the patterning of sub 100nm features. The layer composition of such a TaN absorber consists of an anti reflective coating (ARC) on top of a base layer.
We investigated the dry etch behaviour of TaN based absorbers with four different top ARC layers. Our focus was to determine a dependency of patterning criteria e.g. etch selectivity, minimum resolution, CD uniformity and linearity on the different ARC layers. Before, the deposition parameters of the top ARC layers have been optimized by SCHOTT Lithotec towards minimum stress and the appropriate reflectance property at the 257nm inspection wavelength. The mask blank exposure was done on a 50kV Vistec SB350 MW variable shaped e-beam writer using a 300nm thick Fuji FEP171 resist film. Our test pattern covered a quality area of 132mm x 132mm and comprised dense/iso line structures and contacts from 60nm-1200nm. Testmasks with the four different TaN based absorbers have been dry etched on an Oerlikon mask etcher III. The dry etch recipe and parameters have been kept constant for the different absorber testmasks. Line and contact hole patterns with a minimum feature size of ~70nm and perpendicular profiles have been realized. CD uniformity on 180nm L&S and linearity measurements on dense and iso features from 100nm-1200nm havbe been carried out.
Overall, a TaN based absorber including dry etch process has been developed, able to fulfill the requirements for IC device manufacturing with feature sizes down to 22nm - suitable for EUV-Lithography.
In the framework of the European EXTUMASK project, the Advanced Mask Technology Center in Dresden (AMTC) has established in close collaboration with the Institute of Microelectronics in Stuttgart (IMS-Chips) an integrated mask process suited to manufacture EUV masks for the first full field EUV scanner, the ASML α-demo tool. The first product resulting from this process is the ASML set-up mask, an EUV mask designed to realize the tool set-up.
The integrated process was developed based on dummy EUV blank material received from Schott Lithotec in Meiningen (Germany). These blanks have a TaN-based absorber layer and a SiO2 buffer layer. During process development the e-beam lithographic behaviour as well as the patterning performance of the material were studied and tuned to meet first EUV mask specifications.
For production of the ASML set-up mask the new process was applied to a high performance EUV blank from Schott Lithotec. This blank has absorber and buffer layers identical to the dummy blanks but a multilayer is embedded which is deposited on an LTEM substrate. The actinic behaviour of the multilayer and the flatness of the substrate were tuned to match the required mask specifications. In this article we report on the development of the mask manufacturing process and show performance data of produced EUV full field scanner masks. Thereby, special attention is given to the ASML set-up mask.
A resolution of 45nm dense lines has been be realized in a 100nm thick commercial available positive tone chemically amplified resist (pCAR) using the Leica SB350 variable shaped beam writer. On the basis of this resist process and by optimization of photomask blank material as well as by adaptation of chrome and quartz etching processes, a nanoimprint template technology has been developed which enables patterning of 50nm dense lines. The sensitivity of the selected pCAR as well as the performance of the implemented dynamical stage control of the Leica pattern generator, facilitates an acceptable throughput even for complex pattern. We characterized the templates in terms of feature profile, CD linearity and pattern fidelity. The final imprinting of different pattern proved the applicability of the manufactured stamps for the nanoimprint technology.
Continuous reduction of feature size in semiconductor industry and manufacturing integrated circuits at low costs requires new and innovative technology to overcome existing limitations of optics. Tremendous progress in key areas like EUVL light source technology and manufacturing technology of EUVL masks with low defect rates have been made recently and EUVL is the leading technology capable to be extended so Moore's law, the shrinkage of IC critical features, can continue to be valid. SCHOTT Lithotec has introduced all relevant technology steps to manufacture EUV mask blanks, ranging from Low Thermal Expansion Material (LTEM) with high quality substrate polishing to low defect blank manufacturing. New polishing and cleaning technologies, improved sputter technology and updated metrology enable us to routinely produce EUVL mask blanks meeting already many of the roadmap requirements. Further R&D is ongoing to path the way to the production of EUV blanks which meet all requirements.
An important focus of this paper is to present the recent results on LTEM substrates, which include defect density, roughness and flatness simultaneously, as well as EUVL multilayer properties such as defect density, optical properties like reflectivity and uniformity in the EUV range and optical resistance to cleaning steps. In addition the design of EUVL absorber material will be discussed, including optical performance at EUV wavelength and its contrast behavior.
Finally, IMS Chips has developed the dry etch process of these EUV Mask Blanks by optimizing etch selectivities, profiles and etch bias. Results on CD uniformity, linearity and iso/dense bias will be presented.
We report on a method to produce any type of phase-shift masks for EUV lithography. We have successfully fabricated an unattenuated phase-shift mask consisting of phase patterns and confirmed the expected performance of such a mask through resist printing at λ=13.3 nm. Finally actinic metrology reveals that these etched-multilayer masks, left without a capping layer, tend to degrade over time.
Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm.
Different stacks and manufacturing concepts have been published for the fabrication of the reflective EUVL masks.
Patterning processes for two different absorber-buffer combinations on top of the reflective multi layer mirror have been developed. A TaN/SiO2 absorber-buffer stack was provided by supplier A and TaBN/Cr by supplier B. In addition both absorbers were covered by an anti reflective coating (ARC) layer. An e-beam patterned 300nm thick film of Fuji FEP171 was used as resist mask.
We optimized the etching processes for maximum selectivities between absorber, buffer and capping layers on the one hand and rectangular profiles and low etch bias on the other hand. While both TaN based absorbers have been dry etched in an UNAXIS mask etcher III, wet and dry etch steps have been evaluated for the two different buffer layers. The minimum feature size of lines and holes in our test designs was 100nm.
After freezing the processes a proximity correction was determined considering both, the influence of electron scattering due to e-beam exposure and the influence of the patterning steps. Due to the correction an outstanding linearity and iso/dense bias on different test designs was achieved.
Various masks for printing experiments at the small-field Micro Exposure Tool (MET) in Berkeley and the fabrication of the ASML α-tool setup mask within the European MEDEA+ EXTUMASK project were done using the developed processes.
Finally, we will compare and discuss the results of the two stack approaches.
An initial Nanoimprint template manufacturing process using a state-of-the-art mask front end line has been developed. The process flow is based on conventional 6025 photomask blanks and known basic process steps for chrome and quartz etching. While these etching processes have been slightly adapted, a comprehensive investigation of chemically amplified resists for this purpose was done. We were able to identify a pre-commercial pCAR enabling to approach the 50nm dense line resolution using the Leica SB350 variable shaped beam e-beam writer. We characterized profile, CD-linearity, CD-uniformity and placement accuracy of the nanoimprint templates. The final imprinting of different pattern proved the applicability of the manufactured stamps for the nanoimprint technology.
KEYWORDS: Critical dimension metrology, Scanning electron microscopy, Monte Carlo methods, Extreme ultraviolet, Photomasks, Detection and tracking algorithms, Silicon, Electron beams, Extreme ultraviolet lithography, Signal detection
For extreme ultraviolet lithography (EUVL) the absorber binary mask is until now the most promising mask type. Since at EUV only reflective masks are possible, EUVL will introduce new materials for mask manufacturing. In addition it is likely that the pattern of an EUV mask will consist of a structured double layer system. Therefore, mask CD-SEM metrology for EUVL has to deal with the contrast of rather new materials and has to face a more complex mask pattern topography situation. Using a Monte Carlo model, we simulate the SEM-signals emerging from a given EUV mask pattern topography while scanned by the electron beam of a SEM. The simulation is tuned to closely match the experimental situation of a commercial CD-SEM. Generated SEM images are analyzed by means of a commercial CD-algorithm and a peak detection CD-algorithm. Knowing the exact pattern shape that are fed into the simulation, we determine the effect of specific pattern profile changes on SEM-signal and algorithm specific CD.
Several masks have been fabricated and exposed with the small-field Micro Exposure Tool (MET) at the Advanced Light Source (ALS) synchrotron in Berkeley using EUV radiation at 13.5 nm wavelength. Investigated mask types include two different absorber masks with TaN absorber as well as an etched multilayer mask. The resulting printing performance under different illumination conditions were studied by process window analysis on wafer level. Features with resolution of 60 nm and below were resolved with all masks. The TaN absorber masks with different stack thicknesses showed a similar size of process window. The differences in process windows for line patterns were analyzed for 60 nm patterns. The implications on the choice of optimum mask architecture are discussed.
Three different architectures were compared as candidates for EUV lithography masks. Binary masks were fabricated using two different stacks of absorber materials and using a selective etching process to directly pattern the multilayer of the mask blank. To compare the effects of mask architecture on resist patterning, all three masks were used to print features into photoresist on the EUV micro-exposure tool (MET) at Lawrence Berkeley National Laboratory. Process windows, depth of focus, mask contrast at EUV, and horizontal and vertical line width bias were use as metrics to compare mask architecture. From printing experiments, a mask architecture using a tantalum nitride absorber stack exhibited the greatest depth of focus and process window of the three masks. Experimental results obtained using prototype masks are discussed in relation to simulations. After accounting for CD biasing on the masks, similar performance was found for all three mask architectures.
EUV Lithography requires high end quality defect free layers from the backside coating to the absorber stack. Low thermal expansion materials (LTEM) substrates with super flat surfaces are already available with low defect backside coating for E-Chuck technology. The multilayer stack is well developed from a physical point of view and major effort relies nowadays on the layer defectivity. On the other hand, absorber stack becomes one of the main challenges in terms of stress, optical behavior for ultraviolet wavelengths and dry etching behavior. Schott Lithotec is currently developing absorber stack solutions that will fulfill the requirements of next generation lithographies. There are several options for achieving the mechanical, optical and chemical specs for buffer layers and absorber coatings. Some of them are already integrated in our production processes. Buffer layers were evaluated and reach almost the physical and chemical level necessary to fit with the mask processing. TaN based absorber coatings were designed and deposited by an ion beam sputter tool optimized for low defect deposition (LDD-IBS). The chemical composition of our layer and its manufacturing process is already optimized to achieve high quality etching behavior. The current results of defect density for the absorber stack will be presented.
Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. The SiO2 buffer dry etching is a crucial step in the manufacture of the EUV mask due to stringent CD and reflectance requirements. In contrast to conventional chromium absorber layers new absorber materials e.g. TaN require an adjustment of the SiO2 buffer etch chemistry and process parameters to avoid a strong influence on the initial absorber profile and thickness. We have developed a SiO2 buffer dry etch process that uses the structured TaN absorber as masking layer. A laser reflectometer was used during the SiO2 dry etch process for process control and endpoint detection. Different dry etch processes with SF6/He, CF4 and CHF3/O2 etch chemistry have been evaluated and compared with regard to TaN- and SiO2- etch rate, TaN- and SiO2 etch profile and Si capping layer selectivity. We focused our work on minimum feature sizes and simultaneous etching of different line (e.g. dense- and isolated lines) and hole patterns. Line and contact hole structures with feature sizes down to 100nm have been realized and characterized in a SEM LEO 1560. The whole mask patterning process was executed on an advanced tool set comprising of a Leica SB 350 variable shaped e-beam writer, a blank coater Steag HamaTech ASR5000, a developer Steag HamaTech ASP5000 and a two chamber UNAXIS mask etcher III.
Currently, EUV lithography targets for sub-50 nm features. These very small feature sizes are used for reflective illumination and impose great challenges to the mask maker since they do not allow a simple downscaling of existing technologies. New material combinations for absorber and buffer layer of EUV masks have to be evaluated and fundamental material limits have to be overcome. We report on optimized absorber-stack materials and compare in particular the performance of chrome and tantalum nitride for such small nodes. Tantalum nitride shows similar or even better properties than standard chrome, above all with respect to etch bias. Further investigations have to be done but this material is a promising candidate for feature sizes in the sub-50 nm range.
EUV mask technology poses many new challenges on mask manufacturing processes. One crucial manufacturing step is the patterning of the EUV absorber. Although in the first concepts a Chromium film is used as absorber, increasing demands for shrinking feature sizes will run Chromium out of steam. Due to the necessary oxygen content of the chromium etch plasma and the isotropic etch mechanism for chromium an etch bias of several 10 nm occurs. This results in limitations for the minimal feature size, for which reason a new absorber material has to be developed. The most promising candidate is Tantalum Nitride TaN, which in contrast to the isotropic Cr-etch process, gives the possibility of applying a more anisotropic etch utilizing higher ion energies and sidewall passivation. In this work a plasma etch process for TaN masked with positive CAR resist was developed on masks including a SiO2 buffer layer. Before running the experiments for process characterization, an endpoint detection solution by OES for very small open areas was developed utilizing principal components analysis (PCA). Additionally, an experimental matrix was set up varying bias power, source power and pressure. The DoE experiments were analyzed with respect to etch selectivities, etch bias, etch polymer formation, sidewall angle, iso-dense bias and linearity. After characterisation of the experimental results, optimized process conditions are discussed. We show that this process is capable of resolving feature sizes below 100 nm.
Hans Loeschner, Gerhard Stengl, Herbert Buschbeck, A. Chalupka, Gertraud Lammer, Elmar Platzgummer, Herbert Vonach, Patrick de Jager, Rainer Kaesmaier, Albrecht Ehrmann, Stefan Hirscher, Andreas Wolter, Andreas Dietzel, Ruediger Berger, Hubert Grimm, Bruce Terris, Wilhelm Bruenger, Gerhard Gross, Olaf Fortagne, Dieter Adam, Michael Boehm, Hans Eichhorn, Reinhard Springer, Joerg Butschke, Florian Letzkus, Paul Ruchhoeft, John Wolfe
Recent studies have shown the utility of ion projection lithography (IPL) for the manufacturing of integrated circuits. In addition, ion projection direct structuring (IPDS) can be used for resistless, noncontact modification of materials. In cooperation with IBM Storage Technology Division, ion projection patterning of magnetic media layers has been demonstrated. With masked ion beam proximity techniques, unique capabilities for lithography on nonplanar (curved) surfaces are outlined. Designs are presented for a masked ion beam proximity lithography (MIBL) and masked ion beam direct structuring (MIBS) tool with sub-20-nm resolution capability within 88-mm□ exposure fields. The possibility of extremely high reduction ratios (200:1) for high-volume projection maskless lithography (projection-ML2) is discussed. In the case of projection-ML2 there are advantages of using electrons instead of ions. Including gray scaling, an improved concept for a ⩽50-nm projection-ML2 system is presented with the potential to meet a throughput of 20 wafers per hour (300 mm).
From detailed comparisons of stencil mask distortion measurements with Finite Element (FE) analyses the parameters of influence are well known. Most of them are under control of the mask manufacturer, such as the membrane stress level and the etching process. By means of FE analysis the different contributions may be classified. Some of the errors can be reduced if more stringent specifications of the SOI wafer are fulfilled, some of them may be reduced after pre-calculation. Reduction of the remaining placement errors can be achieved if specific means of an Ion Projection Lithography (IPL) tool are applied. These are mainly magnification and anamorphic corrections removing so-called global distortions. The remaining local distortions can be further reduced by applying the concept of thermal mask adjustment (THEMA).
Positive tone chemically amplified resists CAP209, EP012M (TOK), KRS-XE (JSR) and FEP171 (Fuji) were evaluated for mask making. The investigations were performed on an advanced tool set comprising of a Steag coater ASR5000, Steag developer ASP5000, 50kV e-beam writer Leica SB350, UNAXIS MASK ETCHER III , STS ICP silicon etcher and a CD-SEM KLA8100. We investigated and compared resolution, sensitivity, resist slope, dark field loss, CD-uniformity, line edge roughness, and etch resistance of the evaluated resists. Furthermore, the influence of post coating delay, post exposure delay and other process parameters on the resist performance was determined.
Hans Loeschner, Gerhard Stengl, Herbert Buschbeck, A. Chalupka, Gertraud Lammer, Elmar Platzgummer, Herbert Vonach, Patrick de Jager, Rainer Kaesmaier, Albrecht Ehrmann, Stefan Hirscher, Andreas Wolter, Andreas Dietzel, Ruediger Berger, Hubert Grimm, Bruce Terris, Wilhelm Bruenger, Dieter Adam, Michael Boehm, Hans Eichhorn, Reinhard Springer, Joerg Butschke, Florian Letzkus, Paul Ruchhoeft, John Wolfe
Recent studies carried out with Infineon Technologies have shown the utility of Ion Projection Lithography (IPL) for the manufacturing of integrated circuits. In cooperation with IBM Storage Technology Division the patterning of magnetic films by resist-less Ion Projection Direct Structuring (IPDS) has been demonstrated. With masked ion beam proximity techniques unique capabilities for lithography on non-planar (curved) surfaces are outlined. Designs are presented for a masked ion beam proximity lithography (MIBPL) exposure tool with sub - 20 nm resolution capability within 88 mmo exposure fields. The possibility of extremely high reduction ratios (200:1) for high-volume ion projection mask-less lithography (IP-ML2) is discussed.
Stencil masks, based on 150mm Si-wafers, with large diameter membrane fields have been fabricated for use in an ion projection lithography (IPL) tool. With a current membrane diameter of 126mm, the control of pattern placement is one of the major challenges. As the masks are produced by a wafer flow process, pattern distortions after membrane etch, caused by stiffness changes, have to be controlled. Additionally, stress inhomogenity resulting from SOI wafer blank fabrication, boron implantation and other process steps has to be addressed. These parameters will be discussed on a global and local scale. Results by both, experiments and FE modeling simulations are presented.
A short review of the current status of IPL stencil mask development is presented in this paper. Stencil masks based on 6' Si-wafer have been fabricated with a membrane diameter of 126 mm. With a typical membrane thickness of 3 micrometers , mechanical stability is a critical issue. The resulting placement errors have been measured using an LMS IPRO measurement tool and have been compared to Finite Element (FE) calculations simulating the fabrication process. Process-induced distortions can be predicted by FE calculations with an accuracy of up to 24 mm 3(sigma) . In addition to large circular membranes, an alternative geometry has been considered. Masks with a quadratic membrane area of 60 X 60 mm2 show IPDs of 3(sigma) equals 39 nm which are about 4 times smaller than those of large circular membranes. This result agrees well with predictions of FE calculations. In order to protect the Si-mask against ion bombardment, a protective carbon layer is deposited onto the membrane, thus preventing stress changes due to ion implantation. The current status of the carbon deposition process will also be addressed briefly.
Corresponding to characteristics and manufacturing processes of IPL stencil masks, requirements of used resist technologies are determined. Two thin layer imaging (TLI) techniques, the single layer top surface imaging (TSI) and the bilayer CARL (chemical amplification of resist line) have been investigated and compared for stencil mask making. Especially the process design of CARL is discussed in detail. Additionally, a possible process integration of the carbon layer, that is deposited on the stencil mask and protects the membrane against damaging due to ion bombardment, is presented. Finally, results of silicon etching and complete manufactured stencil masks using the developed resist technologies are demonstrated.
Ion Projection Lithography (IPL) requires stencil masks. These masks are manufactured in a SOI wafer flow process. This means that e-beam patterning and the pattern transfer in silicon is done on the bulk mask-wafer blank before the membrane is formed. The last steps are deposition of a protective carbonic layer and removal of carbon from the stencil openings by etching. The internal stress control of the finally remaining silicon and carbon layers is decisive for the pattern placement accuracy of the stencil mask. The surface geometry and pattern placement are measured with a LEICA LMS IPRO system at different process steps. The initial bow and warp of the SOI mask-wafer blank is measured. Then, the pattern placement is measured after e-beam writing. After membrane formation the samples are measured a third time followed by a final measurement after carbon layer deposition and etch. These results are to be compared with FE (Fenite Elements) modeling calculations. Compared to previous investigations the effect of wafer warp will be included. Furthermore, LMS IPRO measurements will be done with improved tool accuracy on stencil mask membranes as achieved recently. Thus, the claimed functional dependence between stress and pattern distortion is to be verified experimentally.
Stencil masks for Ion Projection Lithography (IPL) are manufactured in a SOI wafer flow process. They consist of a 3 micrometer thick stencil membrane coated by a 0.5 micrometer thick carbonic protection layer. For mask manufacturing, the key parameters which have to be kept under tight control in order to have a high yield are critical dimensions (CD), image placement and defect density. In order to control critical dimensions, the parameters determining CD have to be known in detail. E-beam writing, resist processing, silicon and carbon etching are main contributors. Their impact will be discussed. For CD measurement, different alternatives of tools, optical CD microscopes, AFM and SEM are discussed. Image placement is one of the most critical parameters for IPL stencil masks, as process-induced distortions occur and are to be corrected by a software using FE calculations. Masks usually are specified to 0 defects. Defect inspection results of IPL stencil masks of optical tools are presented, as well as results from e-beam inspection. In addition, defect management for stencil masks in general and cleaning techniques are discussed.
Hardmask-less stencil mask making requires masks with a high aspect ratio. The bilayer CARL (chemical amplification of resist lines) process was evaluated and optimized with respect of generating irregular resist features below 180 nm in a film thickness of 750 nm. Especially the dry development was detailed investigated using statistical design and analysis of experiment. Processed CARL resist masks are compared with Top Surface Imaging results. Finally, results of a deep silicon etching process using the CARL resist masks are presented.
Distortion control is one of the key issues to solve for IPL stencil mask development. Placement is measured by a LEICA LMS IPRO system. Registration as well as overlay results and the error contributions of the measurement will be presented. The production flow of IPL stencil masks is marked by the fact, that e-beam patterning is done on the bulk wafer, whereas the removal of the bulk silicon and the creation of the free membrane takes place at the end of the process, after silicon trench etching. Therefore, distortions appear at the release of the membrane after bulk silicon etching and oxide removal. At e-beam patterning, the mask wafer blank is pre-stressed by the sum of the stresses of the different layers as bulk silicon, silicon oxide, the silicon of the latter membrane and resist. Additionally, the initial warp and bow of the mask wafer blank have to be considered. The analysis of the finite element modeling compares the placement at e-beam writing to the situation after membrane completion. With this information, the efficiency of a FE-supported software correction before mask patterning can be improved. Measurements of masks with different stress values are to be discussed in order to deduce the optimum stress values for IPL stencil masks.
Two process flows for the fabrication of stencil masks have been developed. The PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6 inch Si base wafers with 3 micrometers membrane thickness and a membrane diameter between 120 mm and 126 mm were fabricated. The membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.
Ion beam lithography is one of the most promising future lithography technologies. A helium or hydrogen ion beam illuminates a stencil membrane mask and projects the image with 4X reduction to the wafer. The development of stencil masks is considered to be critical for the success of the new technology. Since 1997, within the European Ion Projection Lithography MEDEA (Microelectronic Devices for European Applications) project silicon stencil masks based on a wafer- flow process are developed. They are produced in a conventional wafer line. Six inch SOI (silicon-on-insulator) wafers are patterned with an e-beam wafer writing tool, then trenches are etched by plasma etching. Afterwards, the membrane is etched by wet etch using the SOI-oxide layer as an etch stop. The last step is to add a coating layer, which is sputtered onto the membrane. It protects the mask against ion irradiation damage. For metrology and inspection, methods used for conventional chromium masks as well as new techniques are investigated. Results from placement measurements on the Leica LMS IPRO tool will be presented. Finally, methods for CD measurement, defect inspection, repair and in-situ-cleaning in the stepper will be discussed, including experimental information of first tests.
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