A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer.
The trends in technology allow the decrease in both size and power consumption of complex digital systems. This decrease in size and power gives rise to new paradigms of computing and use of electronics, with many small devices working collaboratively or at least with strong communication capabilities. Examples of these new paradigms are wearable devices and wireless sensor networks. Currently, these devices are powered by batteries. However, batteries present several disadvantages: the need to either replace or recharge them periodically and their big size and weight compared to high technology electronics. One possibility to overcome these power limitations is to extract (harvest) energy from the environment to either recharge a battery, or even to directly power
the electronic device. This paper presents several methods to design an energy harvesting device depending on the type of energy avaliable.