The effects of electron beam lithography for patterning to the nanoscale a polysilicon layer electrically connected to the gate of an NMOS transistor are investigated by means of the analysis of the transistor current-voltage characteristics. In order to evaluate the impact of the electron beam process, two sets of experiments are carried out. The first set consists in the assessment of the effect on the transistor when directly exposing the polysilicon layer and in the second, the impact of the complete electron beam lithography process is investigated using different acceleration voltages. The results obtained show that a severe degradation of the transistor characteristics occurs when processing at high acceleration voltages. The degradation is observed as a threshold voltage shift and a decrease in the transconductance. This behaviour can be related to positive charge trapping in the gate oxide and generation of interface states at the SiO2-Si interface. In addition unbiased room temperature annealing is found to significantly reduce or compensate the induced positive trapped charges. The results suggest that the secondary radiation created by the primary electron beam is damaging the transistor characteristics and can lead to the loss of circuit performance when using electron beam lithography to fabricate nanostructures in already processed CMOS circuits.
The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever.
Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.