Area scaling without compromising on performance has become a challenge for technology nodes beyond N7. Gate all-around (GAA) device architecture for N5 and beyond technology nodes is emerging as a promising solution and is being heavily investigated by the semiconductor industry. Imec has recently demonstrated that GAA transistor design offers 50% area scaling for both standard cells and SRAM memory cells, by stacking NMOS and PMOS wires on top of each other (also called complimentary FET (CFET)). In addition, design technology co-optimization analysis indicates that CFET architectures meet the N3 power and performance requirements (Ryckaert et.al.; SPIE 2018, VLSI technology symposium 2018). However, integration and fabrication of such CFET architectures become significantly challenging. A primary requirement for GAA (CFET or separate NMOS/PMOS) devices is the formation of silicon channels / nanowires (NW)/nanosheets (NS). For CFET fabrication, a quintessential challenge is an etching method which can provide required selectivity to recess an epitaxially grown material selective to either NMOS or PMOS channel materials into a low-k gate spacer with adequate etch selectivity in an isotropic manner such that stacked wires or sheets can be formed either sequentially or simultaneously.
In the article, we will focus mainly on the Si NW/NS formation (or SiGe etch). Fabricating such NW/NS architecture requires two extremely selective, isotropic, and precise SiGe etches. As shown in Fig.1, step 2 (“SiGe cavity etch”) & step 8 (“channel release”). After the “SiGe cavity etch”, an ALD film of low-k spacer is deposited as the inner spacer (Fig.1, step 3). The SiGe cavity etch (Fig.1, step2) must be controlled with an extreme accuracy and have a straight etch front. The cavity etch will effectively define the inner spacer thickness in the area above and below the Si NW, after the inner spacer etch (step 4, Fig.1). A precise SiGe etch control is essential for the cavity formation, because: (1) if the SiGe recess is below target, the reformed inner spacer thickness will be under specification and may result in high parasitic capacitance between gate and source/drain expected. (2) If the SiGe recess is above target, the reformed inner spacer will penetrate into the replacement gate and will decrease the amount of gate metal wrapping around the nanowire and may impact channel length (Lg). Furthermore, in addition to the above requirements, etch selectivity towards the dummy gate, hard mask, oxide (STI, ILD0), and low K material around the gate (as shown in Fig 1) is essential. We will also demonstrate the process performance for “channel release” as mentioned earlier (Fig 1, step 8) and inner spacer etch (Fig 1, step 4) .To address the requirements described above, a process flow enabled with extremely high selective etches, where the selectivity is a function of film properties and/or etch chemistry is a quintessential advantage. In this article, we will demonstrate the significance of such selective etches for Si NW/NS fabrication.
The switch from dry to immersion lithography has important consequences regarding wafer defectivity. It has been shown
that for successful and efficient defect reductions related to immersion lithography the capability to distinguish
immersion/patterning related defects from stack related defects is very useful during process control. These stack related
defects can be observed after careful partitioning of individual layer inspections and the analysis of this data through DSA in
Klarity. The optimisation of the dark field inspection SP2 tool, central in this paper, shows that improved sensitivity at
adequate signal to noise ratio can be obtained on the resist stacks by using the smaller wavelength as the UV-laser light
present in the SP2. For bare Si and BARC oblique incidence illumination gives the best sensitivity and captures the most
defects. However monitoring of the resist and stacks with resist requires normal incidence illumination since the nature of
defects and film result in a higher scattering intensity using normal illumination. The use of an optical filter and a 10% laser
power also contributed to establishing a lower and stable background signal for each inspection scan. As immersion tool
development is improved and immersion specific defectivity is reduced, the proportion of the stack related defects will
become a significant fraction of the overall target for further defect reduction. This includes point defects (embedded
particles) or flow defects (streaks) identified and classified using SURFimage. Finally this information is to be used to
identify the defect origin(s) for ultimate elimination of defects in the stacks.