Silicon weak pattern exploration becomes more and more attractive for yield improvement and design robustness as these proven silicon weak patterns or hotspots directly reveals process weakness and should be avoided to occur on the chip design. At the very beginning, only a few known hotspot patterns are available as seeds to initialize the weak pattern accumulation process. Machine learning technique can be utilized to expand the weak pattern database, the data volume is critical for machine learning. Fuzzy patterns are built and more potential hotspots locations are found and sent to YE team to confirm, thus more silicon proven data is available for machine learning model training, both good patterns and bad patterns are valuable for the training data set. The trained machine learning model is then used for new hotspots prediction. The outcome from the machine learning prediction need to be validated by silicon data in the first few iterations. When a reliable machine learning model is ready for hotspots detection, designers can run hotspot prediction at the design stage. There are some techniques in training the mode and will be discussed in details in the paper.
It’s desirable to gain high yield and good performance for memory products. Designers have to do some advanced DFM checking on their designs and fix all the critical design issues to be correct by construction before manufacturing. One of the DFM checking items is the litho hotspot checking, LFD (Litho Friendly Design) is the tool adopted for that checking due to its user friendly interface for designers and being able to be integrated with other tools for the advanced checking flow development. One challenge to enable this checking as the signoff item is the long runtime due to the computing-intensive litho simulation. Multiple ways have been figured out to reduce the runtime, for instance, hierarchical checking flow similar to hierarchical design flow under the assumption that many design blocks are reused on the top level; simulation only on the area selected by weak pattern candidates stored in a pattern matching library; simulation only on the unique pattern area by firstly decomposing the layout. All these approaches always tradeoff between runtime and simulation accuracy and come to use with different expectations as the process gradually matures. This paper introduces another technique to reduce the simulation time. This technique is essentially a pattern matching extended application and will be introduced in detail in the paper.