Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.
Growing application of 193nm lithography for low-k1 process has increased the appearance of progressive defects on reticles often known as haze, precipitates or crystal growth. Although the industry has identified multiple potential sources of these progressive defects, a high contributor is a combination of pollutant reactions from reticle manufacturing process and wafer fab environment. This paper will address the analysis of progressive defects and the associated studies focusing on the sources from possible mechanism to prevention methods. In this evaluation, a split study was performed looking at mask cleaning recipes, pellicle types and also the resulting contaminant on the reticles. The reticles were then cycled through 193nm exposure and then inspected on KLA-Tenor's latest best known inspection strategy to capture and characterize the progressive defects. Finally, the mask specification for contamination level, inspection method and re-clean frequency to meet the wafer fab requirements was established. Under these controls, the impact of progressive defects on wafer yield can be minimized.
Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.
From 90nm node and beyond, all of the advanced silicon wafer manufacturing processes are likely to heavily depend on the use of PSM. Two styles of PSM have been considered favorably for both 90nm and 65nm nodes, one is the 6% attenuated PSM and the other one is Chromeless Phase Lithography (CPL) mask. At 65nm node, both of the MoSi-based attenuated PSM and CPL mask are required to be etched into quartz substrate to achieve the desired pi-phase shift. In addition to the demand for very tight top-down mask CD control, for dry-etched process, there are two critical factors can have a significant impact to wafer CD control. They are the etch depth control through feature pitch and the overall etch slope profile. Both contribute to the phase variation. The phase variation degrades the overlapped process window and sufficient phase error can act like spherical lens aberration. This will no doubt impact the wafer imaging performance. In this work, we characterize our dry-etch process by using an orthogonal experiment method and then examine the performance of the optimized recipe by CD metrology, phase uniformity, and actual wafer printing result.
As IC fabrication processes are maturing for the 130nm node, silicon manufacturers are focusing on 90nm device manufacturing at ever-lower k1 factors. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at similar k1 near 0.3. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique. For low-volume, the high mask cost of Alt-PSM discourages its use. What are the most sensible KrF lithography patterning options at k1 = 0.3? For single exposure mask solutions at the 90nm node using KrF, there are two leading candidates: 6% attenuated PSM (Att-PSM) and Chromeless Phase Lithography (CPL). In this work, we explored and compared these two options in terms of the best achievable process latitude for patterning poly gate layer. First, we analyzed the diffraction patterns from 6% Att-PSM and CPL mask features and identified the optimum transmission for various pitches. Next, we examined the two options from a mask making perspective, accessing mask manufacturability, phase and transmission error control, defect sources, etc. In this paper, we describe how hybrid CPL can be used as a variable transmission mask to produce the best through pitch imaging performance and a practical implementation method for mask manufacturing.
In our previously published work, we investigated alternating-aperture PSM image intensity imbalance as function of various mask and optical parameters using rigorous electro-magnetic field (EMF) simulations. Results suggested that the imbalance could be effectively compensated through application of an optimized combination of undercut and a constant phase-shifter bias. In the effort of development and implementation of a production-ready image imbalance correction methodology, it is important to validate the accuracy of simulation-based predictions through correlation of results to experimental data. For this purpose, a test reticle containing various mask parameters as variables was designed and manufactured. The experimental data was obtained from SEM measurements of the exposed wafers, and results were compared to rigorous EMF simulation data. Based on results obtained, we propose and validate an image imbalance correction methodology to be implemented within the framework of the PSM - OPC manufacturing flow.
Double Dipole Lithography (DDL) has been demonstrated to be capable of patterning complex 2D patterns. Due to inherently high aerial imaging contrast, especially for dense features, we have found that it has a very good potential to meet manufacturing requirements for the 65nm node using ArF binary chrome masks. For patterning in the k1<0.35 regime without resorting to hard phase-shift masks (PSMs), DDL is one unique Resolution Enhancement Technique (RET) which can achieve an acceptable process window. To utilize DDL for printing actual IC devices, the original design data must be decomposed into “vertical (V)” and “horizontal (H)” masks for the respective X- and Y-dipole exposures. An improved two-pass, model-based, DDL mask data processing methodology has been established. It is capable of simultaneously converting complex logic and memory mask patterns into DDL compatible mask layout. To maximize the overlapped process window area, we have previously shown that the pattern-shielding algorithm must be intelligently applied together with both Scattering Bars (SBs) and model-based OPC (MOPC). Due to double exposures, stray light must be well-controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of solid chrome in open areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for a typical clear-field poly gate masks to be patterned by a positive resist process. In this work, we report a production-worthy DDL mask pattern decomposition scheme for full-chip application. A new generation of DDL technology reticle set has been developed to verify the printing performance. Shielding is a critical part of the DDL. An innovative shielding scheme has been developed to protect the critical features and minimize the impact of stray light during double exposure.