In order to achieve some special functions, high topography is often introduced in the manufacturing process of chip, which will directly lead to the sharp change of critical dimension (CD), especially for the implant layers post poly process. In this paper, a scheme of reducing the CD range of implant level lithography is proposed. The numerical simulation is carried out through using Fourier optics theory, Fraunhofer diffraction formula and Abbe principle，then the experiment is designed. The simulation results indicate that for advanced process, such as 110nm and 130nm generation, the normalized image logarithmic slope (NILS) of aerial image in the resist on the wafer can be maximized by appropriately increasing numerical aperture (NA) as well as decreasing σ, then the inter-field critical dimension uniformity (CDU) can be greatly improved. The experimental results show that the CD range can be decreased about 41% for the topography of 3000Å, and the better improvement can be achieved for the topography of 1600Å, up to 50%. The research results of this paper provide potential guiding significance for CDU control in implant level lithography process with high topography.