To further improve the characteristics of CMOS image sensors (CIS), we propose a back-side illuminated pixel integrating a vertically pinned and P-type photodiode (which collects holes) and PMOS readout circuitry. It has been designed in a 1.4μm-pitch, a two-transistor (2T) shared readout architecture and fabricated in a combined 65nm and 90nm technology. The vertically pinned photodiode takes up almost the entire volume of the pixel, allowing a full well capacity (FWC) exceeding 7000h+. With a conversion factor around 120μV/h+, the output swing approaching 1V is achieved on the column voltage. The pixel also integrates capacitive deep trench isolation (CDTI) to tackle electrical and optical crosstalk issues. The effective passivation of trench interface by CDTI bias control is demonstrated for a hole-based pixel. As expected, PMOS transistors have much lower trapping noise compared to NMOS counterparts. The PMOS source follower has an average temporal noise of 195μV, mainly dominated by thermal noise contribution.
The CMOS buried multi-junction (BMJ) detector with multiple outputs has distinct spectral responses that may be exploited for applications such as bio-chemical analysis. We tackle here dark current issue by identifying different components inside the detector structure. The identification methods are based on the observation of bias and temperature dependence, as well as measurements of test detector chip integrating different design variations. Surface thermal generation may become predominant when the detector size shrinks, thus causing dark current degradation. To prevent this effect, we propose a low-sized detector structure with passivation of all its surrounding Si/SiO2 interface areas.
Also for the detector readout, we present a multi-channel charge-amplifier architecture with noise analysis. Effects of noise coming from amplifiers and related to the coupled detector’s dynamic conductances are illuminated. To pick up weak signals, synchronous detection can be implemented. A BDJ (Buried Double Junction) detector chip designed with a switched-phase architectural approach gives a minimum detectable signal of 15μlx@555nm or 1μlx@555nm at 27°C or – 10°C, for an integration time of 3s or 45s respectively.