Thin film heads for the hard disk drive industry are fabricated with equipment and processes similar to integrated circuits. One key difference between IC and thin film head (TFH) manufacturing involves the separation of devices following the completion of the wafer-level processing. As a result, the relative placement of individual devices on the wafer, commonly referred to as colinearity, is extremely important and will impact individual device performance and overall yield. Application of advanced KrF step-and-repeat tools is common in TFH manufacturing, but ArF and KrF step-and-scan systems are just being introduced to achieve the imaging performance required for next generation TFH devices. This change will also improve colinearity performance and enable additional degrees of freedom for optimization. Colinearity performance is comprised of individual metrics similar to those in traditional IC overlay budgets with some unique differences. This paper will present error budgets highlighting the photolithographic contributors to colinearity for both step-and-repeat and step-and-scan systems. These budgets will then be populated with experimentally collected performance data for current step-and-repeat and step-and-scan systems. The benefits of step-and-scan colinearity performance relative to that of step-and-repeat will be highlighted along with additional modes of optimization enabled via step-and-scan lithography.
Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch<SUP>2</SUP> regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines a method of quickly estimating colinearity at the wafer-level with a test reticle and metrology equipment routinely found in TFH facilities. Colinearity results are correlated to slider-fab measurements on production devices. Stepper contributions to colinearity are estimated, and compared across multiple steppers and stepper generations. Multiple techniques of integrating this diagnostic into production are investigated and discussed.
Due to the rapid advancements in the data storage market, the development of new technologies and mechanisms are needed to support the continued growth of data storage systems. The concept and technology of Micro Electro Mechanical Systems (MEMS) can provide opportunities to meet these demands. Correspondingly, new MEMS devices can be made commercially available by sharing the benefits of developments in data storage systems. The photolithography requirements for thin film head (TFH) processing have grown increasingly challenging. Specifically, the resolution of submicron isolated features is required in thick photoresist; resulting in aspect ratios of nearly 10 to 1. To satisfy these imaging requirements, the use of i-line reduction lithography tools with variable numerical aperture and partial coherence are necessary. This study examines the influence of NA, (sigma) , and reticle bias on critical features in a typical TFH write-layer process. Combinations of NA and (sigma) were investigated for their impact on minimum feature size, process latitude, and sidewall angle. Process latitude was quantified for each illumination condition over a range of focus and exposure conditions.
As thin film head (TFH) processing advances with magneto resistive (MR) and giant magneto resistive (GMR) designs, the photolithographic requirements for the write portion of the device grow increasingly challenging. Specifically, the resolution of submicron isolated features is required in thick photoresist films; resulting in aspect ratios of nearly 10 to 1. To satisfy the imaging requirements of critical read and write-layers, the use of i-line reduction lithography tools with variable numerical aperture (NA) and partial coherence are necessary. This study examines the influence of NA, (sigma) , and reticle bias on critical feature in typical TFH write-layer processes. Optimal reticle bias was estimated through simulation and confirmed experimentally. Combinations of NA and (sigma) were investigated for their impact on minimum feature size, process latitude, and sidewall angle for multiple resist thicknesses. Process latitude was quantified for each illumination condition over a range of focus and exposure conditions with the use of a low-voltage, automated TFH CD- SEM. A focused ion beam tool and SEM are used to examine wall angels at each of the illumination conditions.
There has been considerable attention given to the printability of reticle defects and their impact on wafer yields. Over the last year the printability risk from small defects increased due to the wider application of optical proximity correction structures and the inclusion of more phase shifting retictles. There have been several simulation studies on the printability of sub-halfmicron defects using lens and illumination parameters of 5X reduction steppers. Since submicron 1X projection systems are being incorporated into numerous fabricant lines, there is a clear need to determine if these system show similar sensitivity to sub- halfmicron defects as reduction steppers. Earlier experimental work examined the printability of several classes of sub-halfmicron 25 micrometers defects on a submicron 1X stepper. To extend this work, a 3D optical lithography simulation tool has been employed to predict the printablity of various reticle defect scenarios. Experimental data was used to validate the 3D simulator by comparing modeling data to SEM measurements of wafers exposed with a reticle containing programmed clear pinhole and opaque pindot defects. A statistically designed simulation study was performed to quantify the critical dimension variation resulting from defects of varying size, proximity to a feature edge and variation in the pitch of the impacted line/space features. An additional statistically designed simulation was then use to predict the printability behavior of defects relative to different features sizes over a range of numerical aperture and partial coherence settings applicable to a 1X lens design. Finally, the impact of defect length and width on printability were characterized for rectangular defects over a range of sizes. Overall, this analysis enhances the understanding of the relationship between reticle defects and 1X projection optics and allows for determination of optical reticle defect specifications for cost effective lithography applications.
A method has been developed that allows accurate simulation of pattern profiles in photoresist in excess of 10 micrometer thick. The method uses the DEPICT<SUP>R</SUP> photolithography simulator to model i-line exposure, bake and development of Shipley SJR<SUP>R</SUP>5740 thick film photoresists with an Ultratech 2244i Wafer Stepper<SUP>R</SUP>. Kim model inputs were estimated from a family of development rate curves obtained by processing wafers with a range of expose energies for logarithmically increasing develop times and measuring thickness change as the develop process occurred. These results were compared with dissolution results obtained using a laser-based dissolution rate monitor. Uncertainties in the measured photoresist absorbence, photosensitivity and refractive index coefficients were estimated and their influence on the simulated results were considered. An optimization procedure and algorithm that allows quantitative comparison of experimental and simulated photoresist profiles is presented. Simulated photoresist profiles were compared with patterns obtained from processed wafers. As a further test of the models, pattern profiles were simulated for 2 micrometer spaces in 10 micrometer thick photoresist through focus. Experimental and simulated pattern profiles from a range of exposure doses were also compared.
As the push for improved resolution in wafer lithography intensifies and 0.18 micrometer devices are nearing production, the potential impact of subhalf micron reticle defects has become a growing concern. There have been several studies on the printability of subhalf-micron defects on high resolution reduction photolithography equipment. These studies have been extended to 1X lithography systems and more recently to advanced sub-micron 1X steppers. Previous studies have indicated that 0.20 micrometer opaque and 0.25 micrometer clear pinhole defects were at the margins of adversely impacting 0.65 micrometer lithography on a 1X stepper. However, due to the limited number of defects at these sizes on the reticle, definitive conclusions on printability could not be drawn. An additional study, using a three dimensional (3D) optical lithography simulation program, has shown defect size, proximity to an adjacent feature, and feature pitch to be significant factors contributing to reticle defect printability. Using the simulation findings as a guide, a new reticle was designed to contain an increased number of clear pinhole and opaque defects in the 0.15 to 0.30 micrometer range located in multiple pitches of both horizontal and vertical line/space pairs. Defect printability was determined using a 1X i-line projection stepper with focus and exposure optimized for nominal critical dimensions of 0.65 micrometer. The reticle and wafer defects were measured using low voltage SEM metrology. Simulation and experimental results have shown that pitch is the most significant contributor in the printability of clear pinhole, opaque, square and aspect ratio defects. In general, the impact of defect proximity to an adjacent feature is less extreme than the effect of pitch, but is more pronounced for clear pinhole defects. This study suggests that simulation can be a useful tool to help lithographers understand the behavior of reticle defects for particular layout design parameters. Consequently, simulation can be used to develop realistic reticle defect specifications with mask vendors, and improve cost-effectiveness. Defect printability simulation can also be used to predict the effect of known defects on existing reticles to determine if these reticles should be used for manufacturing.
There have been several studies on the printability of subhalf-micron defects using reduction steppers. These studies typically involved 1X reticles with defect sizes greater than 0.3 micrometers . Because submicron 1X projection systems are being incorporated into numerous fabrication lines, there is a clear need to determine the impact of subhalf-micron defects using these systems. This paper examines defect detection and measurement capability on 1X reticles and the printability of those defects on production submicron 1X steppers. This analysis will enhance the understanding of the relationship between defect size and 1X projection optics and allows for determination of optimal defect specifications. A test reticle representative of a 64 Mb DRAM metal layer was manufactured with a programmed series of attached and isolated defects ranging from 0.15 to 0.5 micrometers . Both clear and opaque polarity defects were designed. The defects were identified and measured on two different reticle autoinspection systems. The performance of the two systems was compared to the reticle database to evaluate capture rates and efficiency. Actual reticle defect sizes were measured using low voltage SEM metrology. Defect printability was determined using a 1X i-line projection stepper with focus and exposure optimized for nominal critical dimensions (CD). The defects that printed on the wafer were measured and compared to the defects measured on the reticle. The effects of varying wafer exposure dose and focus within a 10 percent CD process window on defect printability were also evaluated. The results of the mask inspection comparison and the reticle versus wafer defect maps are compared.
Modem package designs generate a large amount of stress on the die which can be controlled using a thick film of polyimide over the passivation layer. Polyimide film thicknesses in excess of twenty microns at exposure are becoming common for very thin packages. The standard polyimide lithographic process frequently utilizes a trilayer film consisting of an adhesion layer, a polyimide film, and photoresist. A major advance in polyimide technology occurred with the introduction of photosensitive polyimide materials. These materials reduce the total number of process steps in the polyimide process. They also offer the opportunity to combine the passivation and polyimide lithography steps into one process level resulting in significant process simplification and manufacturing cost reduction. Consequently, there is a rapid increase in the use of photosensitive polyimides in the semiconductor industry. There are a number of important issues associated with photosensitive polyimide processing. Because most photosensitive polyimides are negative tone, residual film formation has a major impact on resolution and the usable process window. The high exposure doses required for thicker polyimide films exacerbates the residual film problem. Also, resolving small features such as fuse windows in DRAMs is frequently required in thick photosensitive polyimide layers. These small features result in polyimide height-to-linewidth aspect ratios that are comparable to many photoresist applications. Because of these requirements, photosensitive polyimide applications could benefit from detailed process characterization to enhance resolution and increase process latitude. Unfortunately, there is scant literature pertaining to lithographic performance and lithographic process modeling for photosensitive polyimide films. An extension of basic photoresist characterization techniques for thin films can be applied to thick photosensitive polyimide processes. The develop rate characteristics and lithographic performance for several commercial photosensitive polyimide products were studied at a thickness of 12 microns. Cross sectional SEM analysis, Bossung plots, and film retention plots are used to establish relative lithographic capabilities. These experimental results are used to study the effects of polyimide physical and chemical properties on lithographic performance.