High aspect ratio beam/trench arrays are etched into silicon substrates using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool. Process input parameters are varied using high/low values for etch cycle time, passivation cycle time, RF power, and SF6 flow rate. The silicon etch process is characterized using photo-resist masked trench arrays varied from 1.5micrometers through 6micrometers in both width and spacing. A design of experiments (DOE) approach is used to model the following measured outputs: 1) trench depth (R2=0.985), 2) lateral trench etch (R2=0.852), 3) trench sidewall angle (R2=0.815), and 4) aspect ratio dependent etch (R2=0.942), where R2 represents the correlation between actual and model predicted values. The presented characterization models are employed to form beams as small as 300nm wide beams etched to a depth >15micrometers with near vertical sidewalls using standard photolithography equipment. In addition, the provided models are exploited to produce a dual re-entrant/tapered beam etch release process. Released silicon beams are demonstrated over 1200micrometers long and 30micrometers thick with a base width of 300nm.
Two closed form algebraic models describing electrostatic latch and release of micro cantilever beams are presented. The 1st model is based on beam theory with a fixed moment at the boundary to represent the electrostatic force and it predicts that electrostatic pull-in occurs at a beam tip displacement of 46% the initial actuator gap. The 2nd model uses a rigid beam pinned at the anchor with a spring equivalent to the beam's mechanical restoring force attached to the tip and describes electrostatic pull-in occurring at a beam tip deflection of 44% the initial actuator gap. Pull-in voltage measurements of polysilicon cantilever beam arrays (6mm wide, 2mm thick, 160 mm long) correlate to both the 1st and 2nd presented models with errors of 8.2% ((sigma) equals1.3%), and 4.9% ((sigma) equals1.4%), respectively. The 1st and 2nd models were observed to improve pull-in voltage prediction by at least 10.3% and 13.7% respectively when compared to previously presented models without the use of empirical correction factors.
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