The leakage power consumption in deep sub-100nm CMOS systems is projected to become a significant part of the total power dissipation. Although the dual Vt CMOS process helps reduce the subthreshold leakage current, the gate leakage problem poses a significant design challenge. We introduce gate leakage tolerant circuits. We describe two new circuit techniques to suppress gate leakage currents in dual Vt Domino circuits. In standby mode, proposed circuits generate low inputs and low outputs for all Domino stages to suppress gate leakage currents in the NMOS logic tree. Simulation results using 45nm BSIM4 SPICE models for 32-bit adders show that adders using the two proposed circuits can reduce the standby gate leakage by 66% and 90%, respectively. Proposed adders have 7% active power overhead to achieve the same speed as single Vt domino adder and the area penalty is minimal with careful layout.
The domino circuit failure is due to competing requirements of the keeper and the NMOS logic transistors that cannot be satisfied simultaneously in order to achieve the noise margin and performance objectives. Domino keeper transistor has to be upsized to compensate for the subthreshold leakage and gate leakage currents that discharge the dynamic node in deep sub-100nm technologies. Domino multiplexer can fail when the fan-in number is greater than 14 for the noise margin of 0.1 Vdd, where the noise margin is defined as the input voltage that causes 10% voltage drop at the dynamic node of Domino. In simulation, 45nm BSIM4 models were used with the power supply voltage of 0.8V. To solve this problem, we propose a dual gate oxide thickness (Tox) implementation for high fan-in Domino. With proper dual gate oxide thickness assignment, subthreshold leakage and gate leakage that discharge the dynamic node are suppressed with the keeper size reduced. Proposed circuit not only prevents the possible failure in high fan-in Domino, but also reduces the delay and power consumption due to decreased contention between the keeper and NMOS logic tree. For 14-bit domino multiplexer, proposed circuit is 56% faster with 66% less power consumption and without area penalty, compared to single Tox domino.