In this paper based on the new parameterization shape, an alternative heavy ion induced soft errors characterization approach is proposed and validated. The method provides an unambiguous calculation procedure to predict an upset rate in highly-scaled memory in a space environment.
In this article, we have studied the influence of Si3N4 and SiO2 thin film gate dielectrics on the current-voltage characteristics of the graphene-based transistor. The test structure of graphene transistor was fabricated with the top and back gate. Graphene has been produced by chemical vapor deposition, and then transferred to the silicon dioxide on a silicon wafer. The channel of the transistor has been formed by etching in oxygen plasma through a photolithographic mask. Metals electrodes of the drain, source, and gate were deposited by resistive evaporation in a vacuum. It was used titanium / aluminum with a thickness of 50/200 nm. In the case of the back gate, silicon dioxide was used, obtained by thermal oxidation of the silicon substrate. For top gate was used silicon nitride deposited by plasma chemical deposition. It was demonstrated that field effect is more pronounced for the case of SiO2 back gate compare to the Si3N4 top gate. For the SiO2 back gate we have observed that the source- drain current decreases, from 2 mA to 3 mA, with increasing the gate voltage, from 0 to 40 V, at constant source-drain voltage, 2 V. In case of Si3N4 top gate the modulation of source-drain current was not significant for the comparable electric field strength. Based on the value of gate voltage for current minima in transfer function the poor quality of Si3N4 –graphene interface is concluded.
It is shown that observed non-monotonic behavior of dose degradation in bipolar devices can be explained within the non-linear set of kinetic equations for the oxide trapped charge and surface recombination centers. It has been shown that proposed earlier a physical model of the Enhanced Low Dose Rate Sensitivity (ELDRS) is fully consistent with experimental temperature dependence of charge yield in thick oxides for a range of low temperatures.
Destructive single event gate rupture (SEGR) occurring in the gate oxides of power MOSFETs under impact of heavy ions is studied and modeled. SEGR cross section of power MOSFET with 70 nm oxide thickness as function of gate voltage was measured for four types of heavy ions. A predictive formula for the SEGR cross section is derived and validated. This formula can be used as a predictive instrument for computation of survival probability in a given spectrum of heavy ions in space environments.
A general approach to derive the current-voltage characteristics both for field-effect and bipolar transistors has been proposed based on exact solution of current continuity equation in diffusion-drift approximation taking into account nonuniformity of electric field and charge density distributions between the contacts. This approach describes in a unified manner both linear and saturation parts of MOSFET’s I-V characteristics as for velocity saturation and for electrostatic pinch-off effect cases. It was shown also that the same design formula is appropriate for description of I-V characteristics in bipolar transistors.