Background: To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These additional degrees of freedom offer better leveling performance, but users hesitate to spend the tool time, wafers, and engineering hours necessary to find and maintain the optimal settings experimentally.
Aim: In order to fully explore the potential of advanced leveling controls, an automated, fast simulation method should be introduced.
Approach: Alternative set-point curves and resulting focus residuals are simulated from existing wafer height maps. Optimizations are carried out to obtain the best edge exclusion settings for several dynamic random access memory and NAND flash memory products, across different layers and exposure tools. The simulated focus errors are compared to the POR settings and verified with electrical results.
Results: An efficient optimization algorithm was demonstrated and significant leveling improvements found for a number of use cases. The resulting settings vary substantially between different products, layers, and exposure tools. The impact of the improved leveling performance is verified using electrical data.
Conclusions: The speed of the presented method proves crucial to help lithographers dial in and maintain numerous settings at optimal values across a typical production line.
To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These can be explored fully with minimum experimental effort by simulating alternative set-point curves (z; Rx; Ry) and resulting MA and MSD focus residuals from existing full wafer height maps. In this paper, optimizations are carried out to obtain the best focus edge clearance settings for several DRAM and NAND products, across different layers and exposure tools. The simulated die-fine focus errors are compared to the POR settings and verified with electrical results. Differences across products, layers, and exposure tools are discussed.
Overlay errors between two layers can be caused by non-lithography processes. While these errors can be compensated by the run-to-run system, such process and tool signatures are not always stable. In order to monitor the impact of non-lithography context on overlay at regular intervals, a systematic approach is needed. Using various machine learning techniques, significant context parameters that relate to deviating overlay signatures are automatically identified. Once the most influential context parameters are found, a run-to-run simulation is performed to see how much improvement can be obtained. The resulting analysis shows good potential for reducing the influence of hidden context parameters on overlay performance. Non-lithographic contexts are significant contributors, and their automatic detection and classification will enable the overlay roadmap, given the corresponding control capabilities.
Before each wafer exposure, the photo lithography scanner’s alignment system measures alignment marks to correct for placement errors and wafer deformation. To minimize throughput impact, the number of alignment measurements is limited. Usually, the wafer alignment does not correct for intrafield effects. However, after calibration of lens and reticle heating, residual heating effects remain. A set of wafers is exposed with special reticles containing many alignment marks, enabling intra-field alignment. Reticles with a dense alignment layout have been used, with different defined intra-field bias. In addition, overlay simulations are performed with dedicated higher order intra-field overlay models to compensate for wafer-to-wafer and across-wafer heating.
Wafer leveling data are usually used inside the exposure tool for ensuring good focus, then discarded. This paper describes the implementation of a monitoring and analysis solution to download these data automatically, together with the correction profiles applied by the scanner. The resulting height maps and focus residuals form the basis for monitoring metrics tailored to catching tool and process drifts and excursions in a high-volume manufacturing (HVM) environment.
In this paper, we present four six cases to highlight the potential of the method: wafer edge monitoring, chuck drift monitoring, correlations between focus residuals and overlay errors, and pre-process monitoring by chuck fingerprint removal.
This paper focuses on orthogonal model corrections where model parameters do not influence each other as long as the
measurement layout is sufficiently symmetric. For the grid correction we used Zernike polynomials, and for the intrafield
correction we used a two-dimensional set of Legendre polynomials. We enabled these corrections by developing a
transformation matrix as an exposure tool is incapable of correcting such orthogonal polynomials. Simulation with
OVALiS shows that the linear parameters get stabilized by several factors when using a combined Zernike/Legendre
model. The correlation between linear and higher order parameters disappears, and overlay mean plus 3-sigma improves
up to ~15–20%. Simulated data agrees well with experimental and electrical data. Additionally, we introduced an
interpolated metric that probed the wafer and field with a dense grid. This interpolated metric showed that the
Zernike/Legendre model-based correction does not cause over-correction like that seen on standard polynomial models.
We have tested higher order process corrections comprehensively by enabling an orthogonal model, as well as by
making use of interpolated metrics to monitor the overlay performance. These orthogonal models can be implemented in
the production line based on inline overlay data where interpolated metrics will ensure that there is no over-correction
and no negative impact on product.
This paper discusses a variety of issues encountered in 193nm lithography high volume production. In order to debug the new 193nm technology, a layer from an older qualified technology was qualified on the new tools. Tool statistics were benchmarked against the installed 248nm tool base. Several issues not known from 248nm lithography or from low volume R&D type pilot runs on 193nm were uncovered. Specifically, issues related to aging of optical parts, defects from various sources, track processing, and masks are discussed.