The PixFEL collaboration has developed the building blocks for an X-ray imager to be used in applications at FELs. In particular, slim edge pixel detectors with high detection efficiency over a broad energy range, from 1 to 12 keV, have been developed. Moreover, a multichannel readout chip, called PFM2 (PixFEL front-end Matrix 2) and consisting of 32 × 32 cells, has been designed and fabricated in a 65 nm CMOS technology. The pixel pitch is 110 μm, the overall area is around 16 mm2. In the chip, different solutions have been implemented for the readout channel, which includes a charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper and an A-to-D converter with a 10 bit resolution. The CSA can be configured in four different gain modes, so as to comply with photon energies in the 1 to 10 keV range. The paper will describe in detail the channel architecture and present the results from the characterization of PFM2. It will discuss the design of a new version of the chip, called PFM3, suitable for post-processing with peripheral, under-pad through silicon vias (TSVs), which are needed to develop four-side buttable chips and cover large surfaces with minimum inactive area.
Cross-talk characterization results of high-fill-factor single-photon avalanche diode (SPAD) arrays in CMOS 150-nm technology are reported and discussed. Three different SPAD structures were designed with two different sizes (15.6 and 25.6 μm pitch) and three guard ring widths (0.6, 1.1, and 1.6 μm). Each SPAD was implemented in an array, composed of 25 (5×5) devices, which can be separately activated. Measurement results show that the average cross-talk probability is well below 1% for the shallow-junction SPAD structure with 15.6 μm pitch and 39.9% fill factor, and 1.45% for the structure with 25.6 μm pitch and 60.6% fill factor. An increase of cross-talk probability with the excess bias voltage is observed.
The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15μm process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.
The design, simulation results and experimental characterization of a compact analog readout circuit for photon counting applications are presented in this paper. Two linear test arrays of 40 pixels with 25 μm pixel pitch have been fabricated in a 0.15 μm CMOS technology. Each pixel of the array consists of a Single-Photon Avalanche Diode (SPAD), a quenching circuit, a time-gating circuit and an analog counter. Each input pulse corresponding to a SPAD avalanche event is converted to a step in the output voltage. Along with compactness, the circuit was designed targeting low power consumption, good output linearity and sub-nanosecond timing resolution. The circuit features 8.6% pixel output nonuniformity and 1.1 % non-linearity. The gating circuit provides the sub-nanosecond window of 0.95 ns at FWHM. Consisting of a small number of transistors and occupying only 238μm2, this approach is suitable for the design of SPAD-based image sensors with high spatial resolution.
In this paper a Time-Of-Flight range camera based on Current Assisted Photonic Demodulators is presented. The sensor,
fabricated in a 0.18 μm CMOS technology, features 120x160 pixel resolution with 10μm pixel pitch and 24% fill factor.
Pixel, camera and system architectures are described highlighting the most important design issues, and a selection of
experimental results is presented. The chip has a power consumption of 200mW, mainly due to the contribution of
modulation current. A range camera system was realized using the proposed sensor, a focusing optics providing a
23°x30° field of view, and a 3-LED illumination module delivering 140mW optical power on the target. The system is
capable of acquiring a stream of 7 3D frames/s with a maximum non-linearity of 3.3% in the range 1.2m-3.7m and a
precision better than 10 cm at 2m and 20 cm at 3m.
This paper presents the simulation modelling of a typical experimental setup for time-resolved fluorescence
measurement. The developed model takes into account the setup geometry, characteristics of light source, detector and
fluorescent sample as well as the adopted measurement technique. A qualitative verification of the model has been
reported before. In this paper, we present a quantitative analysis and verification of the system versatility. For this we
conducted time-resolved fluorescence measurements using a two-chip based micro-system, including a blue micro-LED
array as a light source and a CMOS SPAD array as a detector. The sample of interest (CdSe/ZnS quantum dots in
toluene) in a micro-cavity slide and an excitation filter were placed in the gap between the excitation and detection
planes. A time-correlated single photon counting module was used to build fluorescence decay curves. A range of
experiments with different excitation light pulse widths and using several setups have been performed. The simulated
data are in good agreement with measured results and the model proves to be flexible enough to simulate different light
sources and detector quenching/recharging circuits. This model can be used to predict qualitative and quantitative results
for specific experimental setups, supporting the explanations of observed effects and allowing the realisation of virtual
Fluorescence lifetime detection is widely used in molecular biology to monitor many cell parameters (such as pH, ion
concentrations, etc.) and for an early diagnosis of many pathologies. In a typical fluorescence lifetime experiment a
pulsed laser is used to excite the fluorescent dyes and the emitted light is revealed by means of high sensitivity detectors,
typically: intensified CCD, PMTs or Single-Photon Avalanche Diodes (SPADs).In this contribute we present a SPAD
detector module fabricated in a 0.35μm High Voltage CMOS technology to be used within a lab-on-chip system
consisting of a micro-reactor array for bioaffinity assays based on fluorescence markers. The detector module, having a
total area of 600 x 900 μm2, can be arranged to build a small pixel array to be directly coupled to the micro-reactors. No
emission filters are needed, since the ultra-short laser pulse is cut off in the time domain. The module consists of a
10x10-SPAD array, where each SPAD cell is equipped with dedicated active quenching and recharging circuit. Each cell
has a pitch of 26μm with a fill factor of 48%. The SPADs have been binned in order to realize a large photosensitive area
detector exhibiting a reasonably low dark count rate (DCR) and reduced dead time, as required in a fast measurement
system. A memory has also been implemented in order to enable only low DCR SPADs, so that a total DCR of about
100kHz can be achieved for the whole photosensitive area. The digital output generated by the SPAD array is sent to a
time-discriminator stage which allows a time-gated detection of the incident light. Two time-windows have been
implemented in this architecture. Their time width is controlled by an on-chip digital PLL locked to the external laser
clock whereas the width of the time-windows can be set within the range 500ps-10ns with a resolution of 500ps. Photons
detected within each time window are then counted by two 10-bits digital counters. Time-interleaved operation has been
implemented to read out the pixel data in parallel with the photon detection phase.
This paper describes a simulation model (implemented in MATLAB) of a typical setup used for time-resolved
fluorescence measurements, including: a laser source, basic fluorescence sample, optics, single-photon avalanche diode
and read-out electronics. The correctness of the model has been verified by setting up a simple time-resolved
fluorescence measurement using a CMOS SPAD-based detector. The solution of fluorophore (CdSe/ZnS quantum dots
in toluene) in a glass capillary was placed above the detecting surface and excited by laser pulses. We have used a time-gating
technique with 10-ns observation window shifted at 60-ps time steps across the appropriate time interval. The
observed curve corresponds to the convolution of the fluorescence emission and the 10-ns observation window.
Simulation accuracy has been verified by comparing the experimental fluorescence decay with the simulated one using
chi-square test. The proposed model allows researchers to simulate the behaviour of SPAD detectors with a good
accuracy and demonstrates how imperfections in the experimental system can affect the result. The model enables the
design of SPAD-based detectors with the best performance for a specific application area.