In this paper we present a contribution to create a VHDL-AMS
radio-frequency component library. Currently, integrated circuit
technology tends to integrate in a sole chip not only mixed signal but
also mixed technology systems, going to a more general definition of
the so called Systems On Chip. A library of RF models would be useful
to model, in a same framework, circuits and systems of different
physical domains, including RF, which will certainly optimise design
process of such systems.
Generally, VHDL-AMS, the analogue and mixed signal extension to IEEE
standard VHDL does not include specific formulation for RF devices or
systems modeling, as it does not support distributed parameters for
simulation or description purposes. However, RF devices can be
modeled by means of more general VHDL-AMS resources, like sentences
including algebraic and trigonometric relations.
In this paper, a tool based on free software to perform low level optimization on analog designs is presented. Nowadays, the use of design automation tools for microelectronic circuits design is extending from digital to analog circuits, due in part to the fact that although the analog part of a mixed signal ASIC takes only the 10% of the silicon area, it represents almost 90% of the whole design time. For analog circuits, design process can be divided in two major tasks: topology selection and device sizing. The tool here presented consists on a simulation based optmizh is used to perform automatic low level analog circuit sizing. The tool is composed of three modules: a layout generator, which includes a parasitic extractor, an alaog circuit simulator and a circuit optimizer. The two first modules are respectively Magic and Spice from Berkeley, while the third one, the optimizer, has been developed to evaluate dc, ac, and transient sensitivity simulations performed by Spice and make corrections on the layout sizing. Optimization process starts with a certain topology and standard sized devices, which is then extracted by Magic and simulated by Spice. Performance is evaluated and a sizing correction is proposed. These simulation and corrections are done on an iterative loop until circuit performance reaches design parameters. The tool is demonstrated with an example of a simple analog subcircuit optimization, where parameters like silicon area or power dissipation are optimized, while the circuit keeps on design parameters.
The detection of buried landmines is an important problem in
regions where an army conflict has occurred. In particular, antipersonnel plastic mines cannot be detected with classical techniques, such as metal detectors. So a very promising detection technique based on a thermal model of the soil is applied to detect this kind of mines, in which infrared (IR) images of the soil are used. The core of this technique is the solution of the heat transfer process in the soil and at the soil-air interface, which is a very time consuming process. To overcome this problem we propose an analog circuit which can solve the equations that model the system reducing time cost by taking advantage of the inherent massive parallelism of the circuit. The description of the equations is made with VHDL--AMS and then an automatic synthesis tool generates a circuit which solves the equations.
This paper presents an analog CMOS implementation of a neural
network based on a spinal cord model. The network is comprised by three pairs of cells, Alpha motorneurons, Interneurons and Renshaw cells, which form the basic control motor system for a single limb movement. Behaviour of each neuron is described by a differential equation, which provides it with a dynamic performance. This network is useful to control limb movements based in an antagonist pair of
actuators, i.e. muscles for a human limb or electric motors or SMA fibers for machine applications. This antagonist structure has the main advantage that allows independent control of limb position and stiffness, which makes it suitable for applications where inertial load compensation is a critical factor. For the implementation of the neurons we have developed individual analog operators, like multipliers and integrators, which have been then joined to obtain the cell. The whole circuit works in current mode, and exhibits good
performance in power disipation and bandwidth. The implementation of the network has been done in a 0.35um process from AMS. The layout size is 870 × 480 μm and the power dissipation is 14 mW, using a reference voltage of 3.3 volts. The applications in which this network canbe used fall in two broad cathegories. Firstly, in the development of human-machine interfaces capable to be used both in industry and in handicaped people and secondly in the development o neural controller for industrial robots, providing them with a compliance performance.