An optical highway for parallel interconnection of processors has previously been presented. Several matrix-vector multiplication algorithms are mapped onto the highway, and these are compared with traditional results. The practicalities of implementing such a design are then discussed with attention to possible fabrication routes and the polarization losses involved. This specifically involves mapping the parameter space of the angle of polarizing elements by a Monte Carlo method.
Free-space optical interconnects (FSOIs) are widely seen as a potential solution to present and future bandwidth bottlenecks for parallel processors. We study different topologies that can be implemented using an FSOI system called optical highway (OH). We propose also the use of the rapid prototyping technique as a fast and low-cost tool to implement experimentally different topologies and study their properties. Finally, the rapid prototype designed is used to calculate the maximum number of stages that an optical signal can go through in the OH without the necessity of being regenerated.
A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.