In recent years, directed self-assembly (DSA) has demonstrated tremendous potential to reduce cost for multiple patterning with fewer masks, especially for via patterning. DSA is considered as one of the next generation lithography candidates or complementary lithography techniques to extend 193i lithography further for the sub- 7 nm nodes. In this work, we focus on the simultaneous DSA guiding template assignment and decomposition with DSA and double patterning (DSA-DP) hybrid lithography for 7nm technology node. We first analyze the placement error of DSA patterns with different shapes and sizes. We then propose a graph-based approach to reduce the problem size and solve the problem more efficiently without affecting the optimality of the results. The experimental results demonstrate that we can achieve a 50% reduction in both the number of variables and constraints compared to previous work, which leads to a 50X speed up in runtime.
Standard cell pin access has become one of the most challenging issues for the back-end physical design in sub-14nm technology nodes due to increased pin density, limited number of routing tracks, and complex DFM rules/constraints from multiple patterning lithography. The standard cell I/O pin access problem is very difficult also because the access points of each pin are limited and they interfere with each other. There have been several studies across various standard cell and physical design stages, including standard cell pin access optimization, placement mitigation and routing planning, to achieve overall pin access optimization. In this paper, we will introduce a holistic approach across different design stages to deal with the pin access issue while accommodating the complex DFM constraints in advanced lithography.
For robust standard cell design, designers need to improve the intercell compatibility for all combinations of cells and cell placements. Multiple patterning lithography colorability check breaks the locality of traditional rule check, and N-wise checks are strongly needed to verify the colorability for layout interactions across cell boundaries. A systematic framework is proposed to evaluate the library-level robustness over multiple patterning lithography from two perspectives, including complete checks on two-row combinations of cells and long-range interactions. With complete checks on two-row combinations of cells, the vertical and horizontal boundary checks are explored to predict illegal cell combinations. For long-range interactions, random benchmarks are generated by cell shifting and tested to evaluate the placement-level efforts needed to reduce the manufacturing complexity from quadruple patterning lithography to triple patterning lithography for the middle-of-line (MOL) layers. Our framework is tested on the MOL layers but can be easily adapted to other critical layers with multiple patterning lithography constraints.
Multiple patterning (triple and quadruple patterning) is being considered for use on the Middle-Of-Line (MOL) layers at the 10nm technology node and beyond.1 For robust standard cell design, designers need to improve the inter-cell compatibility for all combinations of cells and cell placements. Multiple patterning colorability checks break the locality of traditional rule checking and N-wise checks are strongly needed to verify the multiple patterning colorability for layout interaction across cell boundaries. In this work, a systematic framework is proposed to evaluate the library-level robustness over multiple patterning from two perpectives, including illegal cell combinations and full chip interactions. With efficient N-wise checks, the vertical and horizontal boundary checks are explored to predict illegal cell combinations. For full chip interactions, random benchmarks are generated by cell shifting and tested to evaluate the placement-level efforts needed to reduce the quadruple patterning to triple patterning for the MOL layer.
New DFM tools appearing on the market hold a promise of assessing parametric and functional
yield loss due to lithography effects. The accuracy of underlying models can limit the veracity
of such assessment. For example, many lithography steps used in the fab are extremely nonlinear
and might exhibit significant differences from models used by the DFM tools.
Furthermore, inputs used in calibrating a model can limit its accuracy, and most organizations
are challenged to characterize the exact needs of a lithography model at a statistically relevant
sampling size. After discussing potential sources of inaccuracy in modeling, the paper will
describe a methodology for modeling and yield prediction based on such accurate modeling.
We discuss the incentive and design outlines for a reticle that is used for assessing across-chip linewidth variation (ACLV). For printing features whose dimensions are near half of the exposure wavelength ((lambda) ), the ACLV Solver reticle can be used to diagnose the contributing factors that cause the critical dimension (CD) to vary out of control. For example, mask error factor (MEF) and mask pattern density loading have both been shown to have a significant impact on ACLV. The focus of this paper is the ACLV design methodology, along with a couple of proposed designs of experiment (DOE). Conclusions and future work are discussed.