The ever increasing pattern densities and design complexities make the tuning of optical proximity correction (OPC) recipes very challenging. One known method for tuning is genetic algorithm (GA). Previously GA has been demonstrated to fine tune OPC recipes in order to achieve better results for possible 1D and 2D geometric concerns like bridging and pinching. This method, however, did not take into account the impact of excess segmentation on downstream operations like fracturing and mask writing.
This paper introduces a general methodology to significantly reduce the number of excess edges in the OPC output, thus reducing the number of flashes generated at fracture and subsequently the write time at mask build. GA is used to reduce the degree of unwarranted segmentation while ensuring good OPC quality. An Objective Function (OF) is utilized to ensure quality convergence and process-variation (PV) plus an additional weighed factor to reduce clustered edge count.
The technique is applied to 14nm metal layer OPC recipes in order to identify excess segmentation and to produce a modified recipe that significantly reduces these segments. OPC output file sizes is shown to be reduced by 15% or more and overall edge count is shown to be reduced by 10% or more. At the same time overall quality of the OPC recipe is shown to be maintained via OPC Verification (OPCV) results.
In this paper we will describe the implementation of a system for model-based verification of post OPC data into a manufacturing data flow. Verification is run automatically, upon OPC completion, on the critical levels for every chip run in the 130nm node and beyond to ensure that OPC errors are caught before hardware is committed in the manufacturing line. The checks are derived from the design rule manual, and are written to cover the intent of the design rules. Some of the challenges of implementing a robust model-based verification solution for manufacturing will be discussed, including resource requirements, data management, cycle time, and the creation of a closed loop system to ensure that verification is completed on all chips. The benefits of implementing model-based verification include improved feedback to lithography and OPC teams, enabling constant improvement, as well as increasing the probability of first time right manufacturing of a new chip design.