VESTIC technology is an alternative for traditional CMOS technology. This paper presents first measurement data of prototypes of VES-BJT: bipolar transistors in VESTIC technology. The VES-BJT is a bipolar transistor on the SOI substrate with symmetric lateral structure and both emitter and collector made of polysilicon. The results indicate that VES-BJT can be a device with useful characteristics. Therefore, VESTIC technology has the potential to become a new BiCMOS-type technology with some unique properties.
In this study, measurements of resistance of polysilicon resistors with different widths have been done over the whole
surface of the SOI wafers. The obtained results have been used to determine changes in their width, which is equivalent
with shortening of the channel length in the photoli-thography process. By studying the elements distributed across the
wafers it was possible to assess the homogeneity of the MOS transistor gate manufacturing process. the abstract two
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