EUV lithography is expected to be introduced in volume manufacturing at the 10-nm and 7-nm node. Especially in these first EUV nodes, critical layer patterning will be balanced with the use of ArF immersion. As a consequence a good overlay and placement matching between both lithography methods becomes an enabling factor for EUV. In this paper we present an integral method to optimize critical layer patterning across the EUV and ArF scanner platform, such that good overlay and device pattern placement is achieved. It is discussed that besides classical overlay control methods, also the optimization of the ArF and EUV imaging steps is needed. Best matching is achieved by applying high-order field-to-field overlay corrections for both imaging and overlay. The lithography architecture we build for these higher order corrections connects the dynamic scanner actuators with the angle resolved scatterometer via a separate computational application server. Improvements of CD uniformity are based on source mask optimization for EUV combined with CD optimization using freeform intra-field dose actuator in the immersion scanner.
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection results on test and production reticles have been validated with AIMS<sup>TM</sup>.
The minimum feature size of integrated circuit continues to shrink. At 32 nm and smaller nodes, mask linearity
errors caused by short range proximity effects less than around 3um during the manufacturing of photomasks
become more significant in the overall lithography error budget. To address this, we have carried out a study that:
(1). models the short range mask error; (2). implements mask process correction (MPC) based on these mask error
models; and (3). verifies the mask process corrections. In this paper we will demonstrate that application of MPC
can significantly reduce mask errors with minimal increase in writing overhead.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to
electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence
effects commonly found in real lithography systems but missing in prior arts. Evaluations against rigorous simulations
and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and
the thick-mask model based on Hopkins treatment of oblique incidence.